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1. 发明申请

WO2009029335A1 DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM 审中-公开
标题翻译：可配置的宽度存储器系统的可互连的互连
公开(公告)号：WO2009029335A1
公开(公告)日：2009-03-05
申请号：PCT/US2008/068822
申请日：2008-06-30
申请人： RAMBUS INC. , KOLLIPARA, Ravindranath , YUAN, Xingchao , LAMBRECHT, Frank , LI, Ming , PEREGO, Richard E. , LIN, Qi , NGUYEN, David , OH, Kyung Suk
发明人： KOLLIPARA, Ravindranath , YUAN, Xingchao , LAMBRECHT, Frank , LI, Ming , PEREGO, Richard E. , LIN, Qi , NGUYEN, David , OH, Kyung Suk
IPC分类号： G06F13/16 , H01L25/10 , H05K1/00
CPC分类号： G06F13/1668 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K1/0237 , H05K1/0295 , H05K1/14 , H05K1/141 , H05K1/147 , H05K3/222 , H05K2201/044 , H05K2201/09954 , H05K2201/10159 , H05K2201/10356
摘要： The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory- controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.
摘要翻译：本公开涉及一种可拆卸信令互连装置，其提供存储器系统的两个或更多个组件与组件的不同操作模式之间的连接。存储器系统包括：第一插座，用于接收第一存储器模块; 用于接收第二存储器模块的第二插座; 可拆卸的信号互连; 以及存储器控制器，其耦合到所述可拆卸信号互连并且被配置为限定第一操作模式和第二操作模式，其中在所述第一操作模式中，所述可拆卸信号互连将所述存储器控制器耦合到所述第一存储器模块，并且在第二操作模式中，可拆卸信号互连将存储器控制器耦合到第一存储器模块和第二存储器模块。

2. 发明申请

WO2011159465A2 BALANCED ON-DIE TERMINATION 审中-公开
标题翻译：平衡点对点终止
公开(公告)号：WO2011159465A2
公开(公告)日：2011-12-22
申请号：PCT/US2011/038656
申请日：2011-06-01
申请人： RAMBUS INC. , WILSON, John , KIM, Joong-Ho , KOLLIPARA, Ravindranath , SECKER, David , OH, Kyung, Suk
发明人： WILSON, John , KIM, Joong-Ho , KOLLIPARA, Ravindranath , SECKER, David , OH, Kyung, Suk
IPC分类号： G11C7/10
CPC分类号： G06F13/4086 , G06F13/4234
摘要： Termination of a high-speed signaling link is effected by simultaneously engaging on- die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.
摘要翻译：高速信令链路的终止通过同时接合设置在同一存储器模块上的多个集成电路存储器件中和/或在相同的集成电路封装内的管芯端接结构来实现，并且耦合到高速信号链路信令链路。

3. 发明申请

WO2009085417A3 MULTI-BAND, MULTI-DROP CHIP TO CHIP SIGNALING 审中-公开
公开(公告)号：WO2009085417A3
公开(公告)日：2009-07-09
申请号：PCT/US2008/083231
申请日：2008-11-12
申请人： RAMBUS INC. , ZERBE, Jared, L. , STOJANOVIC, Vladimir, M. , KOLLIPARA, Ravindranath , BEYENE, Wendemagegnehu , AMIRKHANY, Amir , GARLEPP, Bruno
发明人： ZERBE, Jared, L. , STOJANOVIC, Vladimir, M. , KOLLIPARA, Ravindranath , BEYENE, Wendemagegnehu , AMIRKHANY, Amir , GARLEPP, Bruno
IPC分类号： H04L25/08 , H04L5/06 , G06F13/40
摘要： A system comprising: a first integrated circuit device having a multi-band transmission circuit; second and third integrated circuit devices having respective multi-band reception circuits; and a signaling link including a first stub coupled to the multi-band transmission circuit to receive a multi-band signal therefrom, second and third stubs coupled to the multi-band reception circuits of the second and third integrated circuit devices, respectively, to deliver the multi-band signal thereto, and a plurality of channel segments that extend between the first, second and third stubs to convey the multi-band transmission signal therebetween, and wherein at least one of a physical length, impedance or propagation constant of at least one of the first stub, second stub, third stub or channel segment of the plurality of channel segments is selected to spectrally position a frequency- interval exhibiting attenuated frequency response on the signaling link such that multiple passbands separated by the frequency-interval are established to enable conveyance of the multi-band transmission signal on the signaling link.

4. 发明申请

WO2012109185A3 OFFSETTING CLOCK PACKAGE PINS IN A CLAMSHELL TOPOLOGY TO IMPROVE SIGNAL INTEGRITY 审中-公开
公开(公告)号：WO2012109185A3
公开(公告)日：2012-08-16
申请号：PCT/US2012/024066
申请日：2012-02-07
申请人： RAMBUS INC. , SHAEFFER, Ian , KOLLIPARA, Ravindranath
发明人： SHAEFFER, Ian , KOLLIPARA, Ravindranath
IPC分类号： G11C5/02 , G11C7/10
摘要： The disclosed embodiments relate to the design of a memory system which includes a set of one or more memory modules, wherein each memory module in the set has a clamshell configuration, wherein pairs of opposing memory packages containing memory chips are located on opposite sides of the memory module. The memory system also includes a multi-drop path containing signal lines which pass through the set of memory modules, and are coupled to memory packages in the set of memory modules. For a given signal line in the multi-drop path, a first memory package and a second memory package that comprise a given pair of opposing memory packages are coupled to the given signal line at a first location and a second location, respectively, wherein the first location and the second location are separated from each other by a distance d1 along the given signal line.

5. 发明申请

WO2014062543A2 MEMORY RANK AND ODT CONFIGURATION IN A MEMORY SYSTEM 审中-公开
标题翻译：存储器系统中的存储器排列和ODT配置
公开(公告)号：WO2014062543A2
公开(公告)日：2014-04-24
申请号：PCT/US2013/064781
申请日：2013-10-14
申请人： RAMBUS INC.
发明人： HAN, Minghui , AMIRKHANY, Amir , KOLLIPARA, Ravindranath , SCHMITT, Ralf, Michael
IPC分类号： G11C7/18
CPC分类号： G06F13/28 , G06F3/0611 , G06F3/0635 , G06F3/0683 , G11C5/04 , G11C5/063 , G11C7/1084
摘要： A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.
摘要翻译：存储器系统包括两个存储器模块和存储器控制器。所述存储器模块至少包括对应于第一数量的存储器级别（例如一个存储器级别）的第一存储器包和对应于第二数量的存储器级别（例如，两个存储器级别）的第二存储器包，其大于第一存储器级内存数量排名对于每个模块，存储器封装可以是非对称交错的，使得一个存储器封装比存储器控制器更远于其他存储器封装。存储器控制器经由公共数据线耦合到两个模块的存储器封装，并且产生用于控制存储器封装的片上端接（ODT）的控制信息。

6. 发明申请

WO2013115920A1 MODULATED ON-DIE TERMINATION 审中-公开
标题翻译：调制的在线终端
公开(公告)号：WO2013115920A1
公开(公告)日：2013-08-08
申请号：PCT/US2012/071534
申请日：2012-12-22
申请人： RAMBUS INC.
发明人： AMIRKHANY, Amir , ARYANFAR, Farshid , KOLLIPARA, Ravindranath , YUAN, Xingchao, (chuck)
IPC分类号： G06F13/16
CPC分类号： H03K19/0005 , G06F13/4086 , G11C29/50008 , H03K19/017545 , H04L25/0278
摘要： Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.
摘要翻译：在集成电路器件内施加交替的片上终端阻抗，以将信号反射上变频到由信号通道衰减的较高频率，因为反射向预期信号接收器传播。通过这种方法，相互连接的集成电路器件内的相对较少的开销可以显着降低反射信号的破坏性影响，并且对印刷电路板或其它互连介质几乎没有或没有改变。可以对印刷电路板或其它互连介质进行改变，以进一步增加在上变频反射的频带和感兴趣的信号的传输频带之外的衰减。

7. 发明申请

WO2015164049A1 MEMORY MIRRORING 审中-公开
标题翻译：记忆反射
公开(公告)号：WO2015164049A1
公开(公告)日：2015-10-29
申请号：PCT/US2015/024230
申请日：2015-04-03
申请人： RAMBUS, INC.
发明人： WOO, Steven , SECKER, David , KOLLIPARA, Ravindranath
IPC分类号： G06F12/00
CPC分类号： G06F11/1666
摘要： Memory system enabling memory mirroring in single write operations for primary and backup data storage. In one aspect, the system utilizes a memory channel including one or more latency groups, each encompassing memory modules that have the same signal timing to the controller. A primary and a backup copy of a data element can be written to two memory modules in the same latency group of the channel in a single write operation. In another aspect, a memory channel can store duplicate copies of data into multiple locations disposed in different memory modules and have different data propagation times. The relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay, such that a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.
摘要翻译：内存系统在单次写入操作中启用主镜像和备份数据存储的内存镜像。在一个方面，系统利用包括一个或多个等待时间组的存储器通道，每个延迟组包括与控制器具有相同信号定时的存储器模块。在单次写入操作中，数据元素的主要和备份副本可以写入通道的相同延迟组中的两个内存模块。在另一方面，存储器通道可以将重复的数据副本存储在设置在不同存储器模块中的多个位置，并具有不同的数据传播时间。根据数据传播延迟来调整多个位置之间的芯片选择，命令和地址信号的相对定时，使得数据元素可以响应于从存储器控制器发送的数据信号而写入多个位置传输事件。

8. 发明申请

WO2017023508A1 HIGH PERFORMANCE, HIGH CAPACITY MEMORY MODULES AND SYSTEMS 审中-公开
标题翻译：高性能，高容量存储器模块和系统
公开(公告)号：WO2017023508A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/042356
申请日：2016-07-14
申请人： RAMBUS INC.
发明人： RAJAN, Suresh , ABHYANKAR, Abhijit, M. , KOLLIPARA, Ravindranath , SECKER, David, A.
IPC分类号： G06F3/00
CPC分类号： G06F13/1678
摘要： Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
摘要翻译：描述的是包含地址缓冲器组件和数据缓冲器组件的内存模块，这些组件一起支持宽数据和窄数据模式。地址缓冲器组件管理存储器控制器和两组存储器组件之间的通信。在宽数据模式下，地址缓冲器启用每个集合中的存储器组件，并指示数据缓冲器组件通过组合来自两个集合的数据到每个存储器访问来传送全宽读和写数据。在窄数据模式下，地址缓冲器仅在两组之一中启用存储器组件，并指示数据缓冲器组件对每个存储器访问具有一组半帧读写数据。

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