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1. 发明申请

WO2011097630A2 SYSTEMS AND METHODS PROVIDING ARRANGEMENTS OF VIAS 审中-公开
标题翻译：提供VIAS安排的系统和方法
公开(公告)号：WO2011097630A2
公开(公告)日：2011-08-11
申请号：PCT/US2011/024058
申请日：2011-02-08
申请人： QUALCOMM Incorporated , GU, Shiqun , NOWAK, Matthew Michael , LISK, Durodami J. , TOMS, Thomas R. , RAY, Urmi , SUH, Jungwon , CHANDRASEKARAN, Arvind
发明人： GU, Shiqun , NOWAK, Matthew Michael , LISK, Durodami J. , TOMS, Thomas R. , RAY, Urmi , SUH, Jungwon , CHANDRASEKARAN, Arvind
IPC分类号： H01L25/065
CPC分类号： H01L23/5286 , H01L23/3677 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05093 , H01L2224/13009 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/14505 , H01L2224/16145 , H01L2224/16146 , H01L2224/17517 , H01L2224/48091 , H01L2224/48227 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values.
摘要翻译：半导体芯片包括电连接阵列和将半导体芯片中的至少一个电路耦合到电接触阵列的多个通孔。电触点阵列的电触点中的第一个耦合到N个通孔，并且电触点阵列的电触点中的第二个耦合到M个通孔。 M和N是不同值的正整数。

2. 发明申请

WO2010144848A3 STRESS BALANCE LAYER ON SEMICONDUCTOR WAFER BACKSIDE 审中-公开
公开(公告)号：WO2010144848A3
公开(公告)日：2010-12-16
申请号：PCT/US2010/038383
申请日：2010-06-11
申请人： QUALCOMM Incorporated , GU, Shiqun , CHANDRASEKARAN, Arvind , RAY, Urmi , LI, Yiming
发明人： GU, Shiqun , CHANDRASEKARAN, Arvind , RAY, Urmi , LI, Yiming
IPC分类号： H01L23/00
摘要： A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.

3. 发明申请

WO2010075331A1 EMBEDDED THROUGH SILICON STACK 3-D DIE IN A PACKAGE SUBSTRATE 审中-公开
标题翻译：通过硅包堆叠在包装基板中的三维模具
公开(公告)号：WO2010075331A1
公开(公告)日：2010-07-01
申请号：PCT/US2009/069102
申请日：2009-12-22
申请人： QUALCOMM INCORPORATED , RAY, Urmi , SWEENEY, Fifin , KASKOUN, Kenneth , GU, Shiqun , TOMS, Thomas R.
发明人： RAY, Urmi , SWEENEY, Fifin , KASKOUN, Kenneth , GU, Shiqun , TOMS, Thomas R.
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/5383 , H01L23/5385 , H01L23/5389 , H01L25/03 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： An integrated circuit package has a die or die stack with through silicon vias embedded in a package substrate. A method of producing an integrated circuit package embeds at least one die with a through silicon via in a package substrate. The package substrate provides a protective cover for the die or die stack.
摘要翻译：集成电路封装具有通过硅通孔嵌入封装衬底中的管芯或管芯堆叠。一种制造集成电路封装件的方法在封装衬底中嵌入具有穿硅通孔的至少一个管芯。封装衬底提供用于管芯或管芯堆叠的保护盖。

4. 发明申请

WO2011097464A1 SURFACE PREPARATION OF DIE FOR IMPROVED BONDING STRENGTH 审中-公开
标题翻译：用于改进粘结强度的表面制备
公开(公告)号：WO2011097464A1
公开(公告)日：2011-08-11
申请号：PCT/US2011/023726
申请日：2011-02-04
申请人： QUALCOMM INCORPORATED , CHANDRASEKARAN, Arvind , GU, Shiqun , RAY, Urmi
发明人： CHANDRASEKARAN, Arvind , GU, Shiqun , RAY, Urmi
IPC分类号： H01L21/56 , H01L23/31 , H01L25/065
CPC分类号： H01L23/3142 , H01L21/563 , H01L23/293 , H01L23/3128 , H01L23/3135 , H01L23/3192 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05022 , H01L2224/05147 , H01L2224/0557 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73203 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： A surface preparation method for improved adhesion in an electronic package system. The method of improving adhesion in the electronic package system includes depositing a passivation layer on a bonding surface and roughening at least a portion of the passivation layer. A coating material is deposited on the passivation layer. The bonding surface can be part of a semiconductor or package substrate. The roughening process can be performed by a chemical or mechanical process. In another embodiment, an electronic package system includes a bonding surface of a semiconductor or package substrate. A passivation layer is deposited on the bonding surface and a portion of the passivation layer is roughened for improved adhesion. A coating material is deposited on the roughened portion of the passivation layer.
摘要翻译：一种用于改善电子封装系统中的附着力的表面处理方法。提高电子封装系统中的附着力的方法包括在接合表面上沉积钝化层并使钝化层的至少一部分变粗糙。在钝化层上沉积涂层材料。接合表面可以是半导体或封装衬底的一部分。粗化工艺可以通过化学或机械工艺进行。在另一个实施例中，电子封装系统包括半导体或封装衬底的接合表面。钝化层沉积在接合表面上，钝化层的一部分被粗糙化以提高粘附力。在钝化层的粗糙化部分上沉积涂层材料。

5. 发明申请

WO2011116326A1 THROUGH-SILICON VIA FABRICATION WITH ETCH STOP FILM 审中-公开
标题翻译：通过硅胶制成的薄膜
公开(公告)号：WO2011116326A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/029058
申请日：2011-03-18
申请人： QUALCOMM Incorporated , GU, Shiqun , LI, Yiming , RAY, Urmi
发明人： GU, Shiqun , LI, Yiming , RAY, Urmi
IPC分类号： H01L21/768
CPC分类号： H01L21/76898
摘要： For a semiconductor wafer substrate (102) having an inter layer dielectric (110), a through - silicon via may be formed in the substrate by first depositing an etch stop film (202) on top of the inter layer dielectric, followed by etching an opening (204) through the etch stop film, the interlayer dielectric, and into the substrate. A dielectric liner (206) is then deposited over the etch stop film and into the opening. For some embodiments, the dielectric liner may be etched away except for those portions adhering to the sidewall of the opening. Then a conductive material (208) may be deposited into the opening and on the etch stop film. The excess conductive material may then be removed, and for some embodiments the etch stop film may also be removed.
摘要翻译：对于具有层间电介质（110）的半导体晶片基板（102），可以通过首先在层间电介质的顶部上沉积蚀刻停止膜（202），然后蚀刻通过蚀刻停止膜，层间电介质，并进入衬底的开口（204）。然后将电介质衬垫（206）沉积在蚀刻停止膜上并进入开口中。对于一些实施例，除了粘附到开口的侧壁上的那些部分之外，电介质衬垫可被蚀刻掉。然后可以将导电材料（208）沉积到开口中和蚀刻停止膜上。然后可以除去过量的导电材料，并且对于一些实施例，也可以去除蚀刻停止膜。

6. 发明申请

WO2011009063A1 BARRIER LAYER ON POLYMER PASSIVATION FOR INTEGRATED CIRCUIT PACKAGING 审中-公开
标题翻译：用于集成电路封装的聚合物钝化器的阻挡层
公开(公告)号：WO2011009063A1
公开(公告)日：2011-01-20
申请号：PCT/US2010/042310
申请日：2010-07-16
申请人： QUALCOMM Incorporated , GU, Shiqun , RAY, Urmi , LI, Yiming , CHANDREASKARAN, Arvind
发明人： GU, Shiqun , RAY, Urmi , LI, Yiming , CHANDREASKARAN, Arvind
IPC分类号： H01L23/31 , H01L21/68
CPC分类号： H01L23/3192 , H01L21/6836 , H01L23/3142 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2221/6834 , H01L2224/10126 , H01L2224/1147 , H01L2224/1191 , H01L2224/13022 , H01L2224/13099 , H01L2224/16225 , H01L2224/94 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2224/11 , H01L2224/03
摘要： A barrier layer deposited on the passivation layer of a semiconductor die decreases adhesion of glue used during stacking of semiconductor dies by altering chemical or structural properties of the passivation layer. During detachment of a carrier wafer from a wafer, the barrier layer reduces glue residue on the wafer by modifying the surface of the passivation layer. The barrier layer may be insulating films such as silicon dioxide, silicon nitride, silicon carbide, polytetrafluoroethylene, organic layers, or epoxy and may be less than two micrometers in thickness. Additionally, the barrier layer may be used to reduce topography of the semiconductor die to decrease adhesion of glues.
摘要翻译：沉积在半导体管芯的钝化层上的阻挡层通过改变钝化层的化学或结构特性来降低在半导体管芯堆叠期间使用的胶粘附力。在从晶片分离载体晶片时，阻挡层通过改变钝化层的表面来减少晶片上的胶残余物。阻挡层可以是诸如二氧化硅，氮化硅，碳化硅，聚四氟乙烯，有机层或环氧树脂之类的绝缘膜，并且其厚度可以小于2微米。此外，阻挡层可以用于减少半导体管芯的形貌以降低胶粘剂的粘附。

7. 发明申请

WO2009158287A1 ACTIVE THERMAL CONTROL FOR STACKED IC DEVICES 审中-公开
标题翻译：堆叠IC器件的主动热控制
公开(公告)号：WO2009158287A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048031
申请日：2009-06-19
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew , TOMS, Thomas R.
发明人： GU, Shiqun , NOWAK, Matthew , TOMS, Thomas R.
IPC分类号： H01L25/065 , H01L23/38
CPC分类号： H05K7/20 , H01L23/38 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06589 , H01L2924/00014 , H01L2224/05599
摘要： Thermal conductivity in a stacked IC device (30) can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices (300) can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions (301, 302) created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.
摘要翻译：通过在堆叠的IC器件内构造一个或多个有源温度控制器件，可以提高层叠IC器件（30）中的导热性。在一个实施例中，控制装置是诸如珀耳帖装置之类的热电（TE）装置。然后可根据需要选择性地控制TE器件（300）以去除或加热，以将堆叠的IC器件保持在规定的温度范围内。有源温度控制元件可以是在堆叠的IC器件中产生的P-N结（301,302），并且可以根据需要用于横向和/或垂直地移动热量。

8. 发明申请

WO2010036579A3 LOW COST DIE-TO-WAFER ALIGNMENT/BOND FOR 3D IC STACKING 审中-公开
公开(公告)号：WO2010036579A3
公开(公告)日：2010-04-01
申请号：PCT/US2009/057515
申请日：2009-09-18
申请人： QUALCOMM INCORPORATED , GU, Shiqun , TOMS, Thomas, R.
发明人： GU, Shiqun , TOMS, Thomas, R.
IPC分类号： H01L23/544
摘要： The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.

9. 发明申请

WO2010091096A1 TECHNIQUES FOR PLACEMENT OF ACTIVE AND PASSIVE DEVICES WITHIN A CHIP 审中-公开
标题翻译：在芯片中放置主动和被动设备的技术
公开(公告)号：WO2010091096A1
公开(公告)日：2010-08-12
申请号：PCT/US2010/023070
申请日：2010-02-03
申请人： QUALCOMM INCORPORATED , TOMS, Thomas, R. , NOWAK, Matthew , KIM, Jonghae , GU, Shiqun , HENDERSON, Brian, Matthew
发明人： TOMS, Thomas, R. , NOWAK, Matthew , KIM, Jonghae , GU, Shiqun , HENDERSON, Brian, Matthew
IPC分类号： H01L27/06 , H01L21/768 , H01L23/48 , H01L21/02 , H01L21/98 , H01L23/498
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die (300) includes a semiconductive substrate layer (302) with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices (305) in an active layer (306) on the first side of the semiconductive substrate layer; and a passive device (310) in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs). (321,322).
摘要翻译：半导体管芯（300）包括具有第一和第二侧面的半导体衬底层（302），与半导体衬底层的第二侧相邻的金属层，在有源层（306）上的一个或多个有源器件（305）半导体基片层的第一面; 以及与所述有源层电连通的所述金属层中的无源器件（310）。无源器件可以通过硅通孔（TSV）电耦合到有源层。（321,322）。

10. 发明申请

WO2011044392A1 THREE DIMENSIONAL INDUCTOR AND TRANSFORMER 审中-公开
标题翻译：三维电感和变压器
公开(公告)号：WO2011044392A1
公开(公告)日：2011-04-14
申请号：PCT/US2010/051868
申请日：2010-10-07
申请人： QUALCOMM Incorporated , KIM, Jonghae , GU, Shiqun , HENDERSON, Brian Matthew , TOMS, Thomas R. , CHUA-EOAN, Lew G. , BAZARJANI, Seyfollah S. , NOWAK, Matthew
发明人： KIM, Jonghae , GU, Shiqun , HENDERSON, Brian Matthew , TOMS, Thomas R. , CHUA-EOAN, Lew G. , BAZARJANI, Seyfollah S. , NOWAK, Matthew
IPC分类号： H01L21/02 , H01L23/522 , H01F17/00 , H01L27/06 , H01L23/48
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments (704) of a first metal layer, a plurality of segments (706) of a second metal layer, a first inductor input (708) a second inductor input (710) and a plurality of through silicon vias (702) coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip
摘要翻译：公开了三维片上电感器，变压器和射频放大器。射频放大器包括一对变压器和晶体管。变压器包括至少两个电感耦合电感器。电感器包括第一金属层的多个段（704），第二金属层的多个段（706），第一电感器输入端（708），第二电感器输入端（710）和多个通孔硅通孔（702），耦合所述第一金属层的所述多个段和所述第二金属层的所述多个段，以在所述第一电感器输入和所述第二电感器输入之间形成连续的，不相交的路径。电感器可以具有对称或不对称的几何形状。第一金属层可以是芯片的后端部分中的金属层。第二金属层可以位于芯片的再分布设计层中

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