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1. 发明申请

WO2012119003A1 DISTRIBUTED BUILDING BLOCKS OF R-C CLAMPING CIRCUITRY IN SEMICONDUCTOR DIE CORE AREA 审中-公开
标题翻译：半导体芯片领域R-C钳位电路的分布式建筑块
公开(公告)号：WO2012119003A1
公开(公告)日：2012-09-07
申请号：PCT/US2012/027337
申请日：2012-03-01
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , SIANSURI, Evan , DUNDIGAL, Sreeker, R. , WORLEY, Eugene R.
发明人： JALILIZEINALI, Reza , SIANSURI, Evan , DUNDIGAL, Sreeker, R. , WORLEY, Eugene R.
IPC分类号： H01L27/02
CPC分类号： H01L27/0285 , H01L27/0296 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes resistor-capacitor (RC) clamping circuitry for electrostatic discharge (ESD) protection of the semiconductor die. The RC clamping circuitry includes building blocks distributed in the pad ring and in the core area of the semiconductor die. The building blocks include at least one capacitor block in the core area. The RC clamping circuitry also includes chip level conductive layer connections between each of the distributed building blocks.
摘要翻译：半导体管芯包括用于半导体管芯的静电放电（ESD）保护的电阻 - 电容（RC）钳位电路。 RC钳位电路包括分布在焊盘环和半导体管芯的芯区域中的构建块。构建块包括核心区域中的至少一个电容器块。 RC钳位电路还包括每个分布式构建块之间的芯片级导电层连接。

2. 发明申请

WO2010115137A1 LATERAL DIODE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：横向二极管及其制造方法
公开(公告)号：WO2010115137A1
公开(公告)日：2010-10-07
申请号：PCT/US2010/029830
申请日：2010-04-02
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , WORLEY, Eugene, R. , SIANSURI, Evan , DUNDIGAL, Sreeker, R.
发明人： JALILIZEINALI, Reza , WORLEY, Eugene, R. , SIANSURI, Evan , DUNDIGAL, Sreeker, R.
IPC分类号： H01L21/329 , H01L29/861 , H01L29/06
CPC分类号： H01L29/8611 , H01L29/0692 , H01L29/66128
摘要： An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed.
摘要翻译：可以在没有栅极并且在二极管的掺杂区域之间没有浅沟槽隔离区域的情况下制造具有快导通时间，低电容和低导通电阻的有源二极管。有源二极管中的短导通路径允许快速导通时间，并且缺少栅极氧化物降低有源二极管对极端电压的敏感性。有源二极管可以在集成电路中实现，以防止和减少静电放电（ESD）事件的损坏。有源二极管的制造是通过在盐析之前在二极管的掺杂区域之间沉积自对准硅化物块来实现的。在掺杂区域上形成自对准硅化物层之后，去除硅化物块。

3. 发明申请

WO2012135713A1 DIODE, CIRCUIT EMPLOYING THE SAME AND METHODS OF MANUFACTURE 审中-公开
标题翻译：二极管，采用其的电路和制造方法
公开(公告)号：WO2012135713A1
公开(公告)日：2012-10-04
申请号：PCT/US2012/031597
申请日：2012-03-30
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , WORLEY, Eugene R. , SIANSURI, Evan , DUNDIGAL, Sreeker
发明人： JALILIZEINALI, Reza , WORLEY, Eugene R. , SIANSURI, Evan , DUNDIGAL, Sreeker
IPC分类号： H01L21/329 , H01L29/861 , H01L29/739 , H01L21/33
CPC分类号： H01L29/66356 , H01L27/0255 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H04B1/109 , H04B1/48 , H01L2924/00
摘要： Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.
摘要翻译：提供包括门控二极管和浅沟槽隔离（STI）二极管，制造方法和相关电路的二极管，而不需要至少一个卤素或口袋注入，从而降低二极管的电容。以这种方式，二极管可以用于对负载电容具有敏感性的电路和其它器件，同时仍然获得二极管的性能特性。栅极二极管的这种特性包括快速接通时间和高电导，使得门极二极管非常适合于静电放电（ESD）保护电路。二极管包括具有阱区和其上的绝缘层的半导体衬底。在绝缘层上形成栅电极。阳极和阴极区域设置在阱区中。形成P-N结。在二极管中阻塞至少一个口袋植入物以减少电容。

4. 发明申请

WO2010118350A1 REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY 审中-公开
标题翻译：三维半导体器件接合和组装过程中降低静电放电的可能性
公开(公告)号：WO2010118350A1
公开(公告)日：2010-10-14
申请号：PCT/US2010/030577
申请日：2010-04-09
申请人： QUALCOMM INCORPORATED , HENDERSON, Brian M. , JALILIZEINALI, Reza , GU, Shiqun
发明人： HENDERSON, Brian M. , JALILIZEINALI, Reza , GU, Shiqun
IPC分类号： H01L21/98 , H01L23/60 , H01L25/065 , H01L21/00
CPC分类号： H01L23/488 , H01L21/50 , H01L21/67092 , H01L23/60 , H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06513
摘要： A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device (210/310/410/510) and a ground plane of a second semiconductor device (240/340/440/540 ) to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.
摘要翻译：一种组装堆叠IC器件时降低静电放电敏感性的方法。该方法包括将第一半导体器件（210/310/410/510）的接地平面和第二半导体器件（240/340/440/540）的接地平面耦合到基本相同的电位。第一半导体器件上的有源电路和第二半导体器件上的有源电路在接地平面耦合之后被电耦合。电耦合第一和第二半导体器件的接地平面产生优选的接地静电放电路径，从而最小化对敏感电路元件的潜在损害。

5. 发明申请

WO2010045413A1 ELECTROSTATIC DISCHARGE (ESD) SHIELDING FOR STACKED ICS 审中-公开
标题翻译：用于堆叠ICS的静电放电（ESD）屏蔽
公开(公告)号：WO2010045413A1
公开(公告)日：2010-04-22
申请号：PCT/US2009/060764
申请日：2009-10-15
申请人： QUALCOMM INCORPORATED , TOMS, Thomas R. , JALILIZEINALI, Reza , GU, Shiqun
发明人： TOMS, Thomas R. , JALILIZEINALI, Reza , GU, Shiqun
IPC分类号： H01L25/065 , H01L23/60
CPC分类号： H01L23/60 , H01L25/0657 , H01L2224/274 , H01L2924/01055 , H01L2924/12044
摘要： An unassembled stacked IC device (60) includes an unassembled tier. (41) The unassembled stacked IC device also includes a first unpatterned layer (610) on the unassembled tier. The first unpatterned layer protects the unassembled tier from ESD events.
摘要翻译：未组装的堆叠式IC器件（60）包括未组装的层。（41）未组装的堆叠IC器件还包括在未组装层上的第一未图案化层（610）。第一个无图案层保护未组装的层免受ESD事件的影响。

6. 发明申请

WO2010019663A1 SYSTEM AND METHOD FOR EXCESS VOLTAGE PROTECTION IN A MULTI-DIE PACKAGE 审中-公开
标题翻译：用于多模封装中过电压保护的系统和方法
公开(公告)号：WO2010019663A1
公开(公告)日：2010-02-18
申请号：PCT/US2009/053548
申请日：2009-08-12
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , DUNDIGAL, Sreeker , MOHAN, Vivek
发明人： JALILIZEINALI, Reza , DUNDIGAL, Sreeker , MOHAN, Vivek
IPC分类号： H01L23/60 , H01L25/065
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.
摘要翻译：在多管芯封装的一个管芯上实现的保护系统为封装的一个或多个其它管芯上产生的过电压提供放电路径。为封装中的某些电路提供接地路径，这些电路具有高噪声灵敏度，并且为封装中的某些电路提供了相对于高噪声敏感度电路具有低噪声灵敏度的接地路径。多个芯片的高噪声敏感度电路的接地短路在一起，产生了一个共同的高噪声敏感性接地。多芯片的低噪声敏感电路的接地短路在一起，产生一个共同的低噪声敏感性接地。在芯片外部的封装上包含预先指定的可移除路径，这样可以使公共高噪声敏感地和公共低噪声敏感地面短路。如果存在于短路接地上的噪声导致不可接受的性能下降，则在制造过程中可移除路径。

7. 发明申请

WO2010068490A8 DIE-TO-DIE POWER CONSUMPTION OPTIMIZATION 审中-公开
公开(公告)号：WO2010068490A8
公开(公告)日：2010-06-17
申请号：PCT/US2009/065890
申请日：2009-11-25
申请人： QUALCOMM INCORPORATED , BAZARJANI, Seyfi , JALILIZEINALI, Reza
发明人： BAZARJANI, Seyfi , JALILIZEINALI, Reza
IPC分类号： H01L27/02 , H01L23/60 , H01L25/065
摘要： Power consumption of electronic components is reduced, particularly in a multi-chip package. Embodiments reduce parasitic capacitance of a semiconductor chip by reducing ESD protection circuitry that is not needed during operation of the package. ESD protection circuitry would be operational during production and/or testing of the chip, but some circuitry would be disabled or removed prior to normal operation of the multi-chip package.

8. 发明申请

WO2010014408A2 METHOD AND APPARATUS FOR FORMING I/O CLUSTERS IN INTEGRATED CIRCUITS 审中-公开
标题翻译：在集成电路中形成I / O集群的方法和装置
公开(公告)号：WO2010014408A2
公开(公告)日：2010-02-04
申请号：PCT/US2009/050752
申请日：2009-07-15
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , DUNDIGAL, Sreeker , MOHAN, Vivek , TOMS, Thomas, R.
发明人： JALILIZEINALI, Reza , DUNDIGAL, Sreeker , MOHAN, Vivek , TOMS, Thomas, R.
IPC分类号： H01L27/092 , H01L27/02 , H03K17/0814 , H01L23/485
CPC分类号： H01L27/0921 , H01L21/823871 , H01L23/50 , H01L24/02 , H01L27/0207 , H01L27/0266 , H01L2924/14 , H01L2924/3025 , H03K19/00315 , Y10T29/49117
摘要： A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.
摘要翻译：第一I / O焊盘具有设置在第一I / O焊盘的第一端的第一型晶体管。第二I / O焊盘具有设置在第二I / O焊盘的第一端的另一第一型晶体管。第一I / O焊盘的第一端邻接第二I / O焊盘的第一端，因此第一型晶体管与另一第一型晶体管相邻。

9. 发明申请

WO2016137639A1 OUTPUT DRIVER WITH BACK-POWERING PREVENTION 审中-公开
标题翻译：输出驱动器具有备用电源预防
公开(公告)号：WO2016137639A1
公开(公告)日：2016-09-01
申请号：PCT/US2016/014990
申请日：2016-01-26
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wilson Jianbo , TAN, Chiew-Guan , JALILIZEINALI, Reza
IPC分类号： H03K19/003
CPC分类号： H03K17/26 , H03K17/18 , H03K19/00315 , H03K19/00361
摘要： A back-power prevention circuit (205) is provided that protects a buffer transistor (MPl) from back-power during a back-power condition by charging a signal lead (PCLT) coupled to a gate of the buffer transistor (MPl), to a pad voltage (PadSig) and by charging a body (235) of the buffer transistor (MPl) to the pad voltage (PadSig, NW).
摘要翻译：提供了一种背功率防止电路（205），其通过对耦合到缓冲晶体管（MP1）的栅极的信号引线（PCLT）进行充电来在后功率状态期间保护缓冲晶体管（MP1）免于后功率，垫片电压（PadSig），并通过将缓冲晶体管（MP1）的主体（235）充电到焊盘电压（PadSig，NW）。

10. 发明申请

WO2015047554A1 MIXED MODE RC CLAMPS 审中-公开
标题翻译：混合模式RC CLAMPS
公开(公告)号：WO2015047554A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/050162
申请日：2014-08-07
申请人： QUALCOMM INCORPORATED
发明人： WORLEY, Eugene Robert , JALILIZEINALI, Reza , DUNDIGAL, Sreeker
IPC分类号： H01L27/02 , H02H9/04
CPC分类号： H01L23/60 , H01L27/0285 , H01L27/0682 , H01L2924/0002 , H02H9/046 , H01L2924/00
摘要： A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant.
摘要翻译：系统互连包括具有第一RC时间常数的第一电阻器 - 电容（RC）钳位。系统互连还包括具有第二RC时间常数的第二RC钳位。第一和第二RC夹具沿着系统互连排列。另外，第一RC时间常数与第二RC时间常数不同。

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