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1. 发明申请

WO2015047554A1 MIXED MODE RC CLAMPS 审中-公开
标题翻译：混合模式RC CLAMPS
公开(公告)号：WO2015047554A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/050162
申请日：2014-08-07
申请人： QUALCOMM INCORPORATED
发明人： WORLEY, Eugene Robert , JALILIZEINALI, Reza , DUNDIGAL, Sreeker
IPC分类号： H01L27/02 , H02H9/04
CPC分类号： H01L23/60 , H01L27/0285 , H01L27/0682 , H01L2924/0002 , H02H9/046 , H01L2924/00
摘要： A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant.
摘要翻译：系统互连包括具有第一RC时间常数的第一电阻器 - 电容（RC）钳位。系统互连还包括具有第二RC时间常数的第二RC钳位。第一和第二RC夹具沿着系统互连排列。另外，第一RC时间常数与第二RC时间常数不同。

2. 发明申请

WO2017209834A1 BULK CROSS-COUPLED HIGH DENSITY POWER SUPPLY DECOUPLING CAPACITOR 审中-公开
标题翻译：散装交叉耦合高密度电源解耦电容器
公开(公告)号：WO2017209834A1
公开(公告)日：2017-12-07
申请号：PCT/US2017/024798
申请日：2017-03-29
申请人： QUALCOMM INCORPORATED
发明人： KUMAR, Albert , DANG, Hai , DUNDIGAL, Sreeker , VADI, Vasisht
IPC分类号： H01L27/02 , H01L27/08 , H01L27/092
摘要： In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device includes a pMOS transistor (202) and an nMOS transistor (204). The MOS device includea a first set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The first set of transistor body connections couples a first voltage source (Vdd) to the pMOS transistor body (202b). The first set of transistor body connections further couples a second voltage source (Vss) to the nMOS transistor body (204b). The MOS device includes a second set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The second set of transistor body connections couples the nMOS transistor gate (204g) to the pMOS transistor body (202b). The second set of transistor body connections further couples the pMOS transistor gate (202g) to the nMOS transistor body (204b).
摘要翻译：在本公开的一个方面中，提供了一种用于使用体交叉耦合薄氧化物去耦电容器的MOS器件。 MOS器件包括pMOS晶体管（202）和nMOS晶体管（204）。 MOS器件包括与pMOS晶体管和nMOS晶体管相邻的第一组晶体管本体连接。第一组晶体管本体连接将第一电压源（Vdd）耦合到pMOS晶体管本体（202b）。第一组晶体管本体连接还将第二电压源（Vss）耦合到nMOS晶体管本体（204b）。 MOS器件包括与pMOS晶体管和nMOS晶体管相邻的第二组晶体管连接。第二组晶体管本体连接将nMOS晶体管栅极（204g）耦合到pMOS晶体管本体（202b）。第二组晶体管本体连接还将pMOS晶体管栅极（202g）耦合到nMOS晶体管本体（204b）。

3. 发明申请

WO2018151956A1 DIE-TO-DIE INTERFACE CONFIGURATION AND METHODS OF USE THEREOF 审中-公开
公开(公告)号：WO2018151956A1
公开(公告)日：2018-08-23
申请号：PCT/US2018/016730
申请日：2018-02-02
申请人： QUALCOMM INCORPORATED
发明人： DUBOWSKI, Kenneth , PETERSON, Luverne Ray , BRYAN, Thomas , KNOL, Stephen , DUNDIGAL, Sreeker , LOKE, Alvin Leng Sun
IPC分类号： H03K19/0175
摘要： A semiconductor die including: a die-to-die interface including an input /output (I/O) circuitry area and an electrical contact area; wherein the electrical contact area includes an array of electrical contacts disposed on a side of the semiconductor die; and wherein the I/O circuitry area includes a plurality of drivers, each of the drivers coupled to at least one electrical contact in the electrical contact area, and a plurality of electrostatic discharge (ESD) protection devices, each of the ESD protection devices coupled to a respective driver, further wherein the I/O circuitry area and the electrical contact area are separated in a top-down view of the semiconductor die.

4. 发明申请

WO2010019663A1 SYSTEM AND METHOD FOR EXCESS VOLTAGE PROTECTION IN A MULTI-DIE PACKAGE 审中-公开
标题翻译：用于多模封装中过电压保护的系统和方法
公开(公告)号：WO2010019663A1
公开(公告)日：2010-02-18
申请号：PCT/US2009/053548
申请日：2009-08-12
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , DUNDIGAL, Sreeker , MOHAN, Vivek
发明人： JALILIZEINALI, Reza , DUNDIGAL, Sreeker , MOHAN, Vivek
IPC分类号： H01L23/60 , H01L25/065
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.
摘要翻译：在多管芯封装的一个管芯上实现的保护系统为封装的一个或多个其它管芯上产生的过电压提供放电路径。为封装中的某些电路提供接地路径，这些电路具有高噪声灵敏度，并且为封装中的某些电路提供了相对于高噪声敏感度电路具有低噪声灵敏度的接地路径。多个芯片的高噪声敏感度电路的接地短路在一起，产生了一个共同的高噪声敏感性接地。多芯片的低噪声敏感电路的接地短路在一起，产生一个共同的低噪声敏感性接地。在芯片外部的封装上包含预先指定的可移除路径，这样可以使公共高噪声敏感地和公共低噪声敏感地面短路。如果存在于短路接地上的噪声导致不可接受的性能下降，则在制造过程中可移除路径。

5. 发明申请

WO2022005832A1 CIRCUIT TECHNIQUES FOR ENHANCED ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS 审中-公开
公开(公告)号：WO2022005832A1
公开(公告)日：2022-01-06
申请号：PCT/US2021/038623
申请日：2021-06-23
申请人： QUALCOMM INCORPORATED
发明人： DUNDIGAL, Sreeker , JALILIZEINALI, Reza , CHILLARA, Krishna Chaitanya , CHEN, Wen-Yi
IPC分类号： H01L27/02 , H02H9/04 , G06F30/36 , G06F30/367 , G06F30/3953 , H01L27/0255 , H01L27/0292 , H03H7/38
摘要： A chip includes a pad and a driver having an output coupled to the pad. The chip also includes one or more diodes coupled between the pad and a ground bus, wherein the one or more diodes are in a forward direction from the pad to the ground bus.

6. 发明申请

WO2017172002A1 ELECTROSTATIC DISCHARGE (ESD) ISOLATED INPUT/OUTPUT (I/O) CIRCUITS 审中-公开
标题翻译：静电放电（ESD）隔离输入/输出（I / O）电路
公开(公告)号：WO2017172002A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/014949
申请日：2017-01-25
申请人： QUALCOMM INCORPORATED
发明人： WORLEY, Eugene Robert , JALILIZEINALI, Reza , DUNDIGAL, Sreeker , CHEN, Wen-Yi , CHILLARA, Krishna Chaitanya , KANG, Taeghyun
IPC分类号： H03K19/003 , H03K19/0185
摘要： A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal (102) from a pair of I/O transistors of the SERDES differential I/O circuit (120) in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal (104) from the pair of I/O transistors of the SERDES differential I/O circuit (120) in response to the detected electrostatic discharge event.
摘要翻译：保护串行器/解串器（SERDES）差分输入/输出（I / O）电路的方法包括检测静电放电事件。该方法还包括响应于检测到的静电放电事件，选择性地使电源端子（102）与SERDES差分I / O电路（120）的一对I / O晶体管分离。该方法还包括响应于检测到的静电放电事件选择性地将接地端子（104）与SERDES差分I / O电路（120）的一对I / O晶体管分离。

7. 发明申请

WO2012135713A1 DIODE, CIRCUIT EMPLOYING THE SAME AND METHODS OF MANUFACTURE 审中-公开
标题翻译：二极管，采用其的电路和制造方法
公开(公告)号：WO2012135713A1
公开(公告)日：2012-10-04
申请号：PCT/US2012/031597
申请日：2012-03-30
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , WORLEY, Eugene R. , SIANSURI, Evan , DUNDIGAL, Sreeker
发明人： JALILIZEINALI, Reza , WORLEY, Eugene R. , SIANSURI, Evan , DUNDIGAL, Sreeker
IPC分类号： H01L21/329 , H01L29/861 , H01L29/739 , H01L21/33
CPC分类号： H01L29/66356 , H01L27/0255 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H04B1/109 , H04B1/48 , H01L2924/00
摘要： Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.
摘要翻译：提供包括门控二极管和浅沟槽隔离（STI）二极管，制造方法和相关电路的二极管，而不需要至少一个卤素或口袋注入，从而降低二极管的电容。以这种方式，二极管可以用于对负载电容具有敏感性的电路和其它器件，同时仍然获得二极管的性能特性。栅极二极管的这种特性包括快速接通时间和高电导，使得门极二极管非常适合于静电放电（ESD）保护电路。二极管包括具有阱区和其上的绝缘层的半导体衬底。在绝缘层上形成栅电极。阳极和阴极区域设置在阱区中。形成P-N结。在二极管中阻塞至少一个口袋植入物以减少电容。

8. 发明申请

WO2023283009A1 INTERFACE CIRCUIT WITH ROBUST ELECTROSTATIC DISCHARGE 审中-公开
公开(公告)号：WO2023283009A1
公开(公告)日：2023-01-12
申请号：PCT/US2022/032388
申请日：2022-06-06
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wen-Yi , JALILIZEINALI, Reza , DUNDIGAL, Sreeker , CHILLARA, Krishna Chaitanya , LYNCH, Gregory
IPC分类号： H01L27/02 , H03K19/003
摘要： An ESD protection circuit has a driver transistor with a drain that is coupled to an input/output (I/O) pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad and a low impedance path when an overvoltage signal is applied to the I/O pad.

9. 发明申请

WO2022005831A1 CIRCUIT TECHNIQUES FOR ENHANCED ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS 审中-公开
公开(公告)号：WO2022005831A1
公开(公告)日：2022-01-06
申请号：PCT/US2021/038620
申请日：2021-06-23
申请人： QUALCOMM INCORPORATED
发明人： DUNDIGAL, Sreeker , JALILIZEINALI, Reza , CHILLARA, Krishna Chaitanya , CHEN, Wen-Yi
IPC分类号： H01L27/02 , H02H9/04 , H03K19/003 , H01L27/0255 , H01L27/0266 , H01L27/0288 , H01L27/0292 , H02H1/0007 , H02H9/046 , H03K17/0822 , H03K19/00315
摘要： Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.

10. 发明申请

WO2010014408A2 METHOD AND APPARATUS FOR FORMING I/O CLUSTERS IN INTEGRATED CIRCUITS 审中-公开
标题翻译：在集成电路中形成I / O集群的方法和装置
公开(公告)号：WO2010014408A2
公开(公告)日：2010-02-04
申请号：PCT/US2009/050752
申请日：2009-07-15
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , DUNDIGAL, Sreeker , MOHAN, Vivek , TOMS, Thomas, R.
发明人： JALILIZEINALI, Reza , DUNDIGAL, Sreeker , MOHAN, Vivek , TOMS, Thomas, R.
IPC分类号： H01L27/092 , H01L27/02 , H03K17/0814 , H01L23/485
CPC分类号： H01L27/0921 , H01L21/823871 , H01L23/50 , H01L24/02 , H01L27/0207 , H01L27/0266 , H01L2924/14 , H01L2924/3025 , H03K19/00315 , Y10T29/49117
摘要： A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.
摘要翻译：第一I / O焊盘具有设置在第一I / O焊盘的第一端的第一型晶体管。第二I / O焊盘具有设置在第二I / O焊盘的第一端的另一第一型晶体管。第一I / O焊盘的第一端邻接第二I / O焊盘的第一端，因此第一型晶体管与另一第一型晶体管相邻。

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