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1. 发明申请

WO2012119003A1 DISTRIBUTED BUILDING BLOCKS OF R-C CLAMPING CIRCUITRY IN SEMICONDUCTOR DIE CORE AREA 审中-公开
标题翻译：半导体芯片领域R-C钳位电路的分布式建筑块
公开(公告)号：WO2012119003A1
公开(公告)日：2012-09-07
申请号：PCT/US2012/027337
申请日：2012-03-01
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , SIANSURI, Evan , DUNDIGAL, Sreeker, R. , WORLEY, Eugene R.
发明人： JALILIZEINALI, Reza , SIANSURI, Evan , DUNDIGAL, Sreeker, R. , WORLEY, Eugene R.
IPC分类号： H01L27/02
CPC分类号： H01L27/0285 , H01L27/0296 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes resistor-capacitor (RC) clamping circuitry for electrostatic discharge (ESD) protection of the semiconductor die. The RC clamping circuitry includes building blocks distributed in the pad ring and in the core area of the semiconductor die. The building blocks include at least one capacitor block in the core area. The RC clamping circuitry also includes chip level conductive layer connections between each of the distributed building blocks.
摘要翻译：半导体管芯包括用于半导体管芯的静电放电（ESD）保护的电阻 - 电容（RC）钳位电路。 RC钳位电路包括分布在焊盘环和半导体管芯的芯区域中的构建块。构建块包括核心区域中的至少一个电容器块。 RC钳位电路还包括每个分布式构建块之间的芯片级导电层连接。

2. 发明申请

WO2012135713A1 DIODE, CIRCUIT EMPLOYING THE SAME AND METHODS OF MANUFACTURE 审中-公开
标题翻译：二极管，采用其的电路和制造方法
公开(公告)号：WO2012135713A1
公开(公告)日：2012-10-04
申请号：PCT/US2012/031597
申请日：2012-03-30
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , WORLEY, Eugene R. , SIANSURI, Evan , DUNDIGAL, Sreeker
发明人： JALILIZEINALI, Reza , WORLEY, Eugene R. , SIANSURI, Evan , DUNDIGAL, Sreeker
IPC分类号： H01L21/329 , H01L29/861 , H01L29/739 , H01L21/33
CPC分类号： H01L29/66356 , H01L27/0255 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H04B1/109 , H04B1/48 , H01L2924/00
摘要： Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.
摘要翻译：提供包括门控二极管和浅沟槽隔离（STI）二极管，制造方法和相关电路的二极管，而不需要至少一个卤素或口袋注入，从而降低二极管的电容。以这种方式，二极管可以用于对负载电容具有敏感性的电路和其它器件，同时仍然获得二极管的性能特性。栅极二极管的这种特性包括快速接通时间和高电导，使得门极二极管非常适合于静电放电（ESD）保护电路。二极管包括具有阱区和其上的绝缘层的半导体衬底。在绝缘层上形成栅电极。阳极和阴极区域设置在阱区中。形成P-N结。在二极管中阻塞至少一个口袋植入物以减少电容。

3. 发明申请

WO2010053791A1 AMPLIFIER WITH IMPROVED ESD PROTECTION CIRCUITRY 审中-公开
标题翻译：具有改进的ESD保护电路的放大器
公开(公告)号：WO2010053791A1
公开(公告)日：2010-05-14
申请号：PCT/US2009/062409
申请日：2009-10-28
申请人： QUALCOMM Incorporated , WORLEY, Eugene R.
发明人： WORLEY, Eugene R.
IPC分类号： H03F1/52 , H03F3/45 , H03F3/195 , H01L27/02
CPC分类号： H03F1/523 , H01L27/0255 , H03F3/195 , H03F3/45183 , H03F2200/294 , H03F2200/441 , H03F2200/444 , H03F2200/492 , H03F2203/45314 , H03F2203/45386 , H03F2203/45568
摘要： An amplifier (e.g., an LNA) with improved ESD protection circuitry is described. In one exemplary design, the amplifier includes a transistor (410), an inductor (412), and a clamp circuit (422). The transistor (410) has a gate coupled to a pad (450) and provides signal amplification for the amplifier. The inductor (412) is coupled to a source of the transistor (410) and provides source degeneration for the transistor (410). The clamp circuit (422) is coupled between the gate and source of the transistor (410) and provides ESD protection for the transistor (410). The clamp circuit (422) may include al least one diode coupled between the gale and source of the transistor (410). The clamp circuit (422) conducts current through the inductor (412) to generate a voltage drop across the inductor (412) when a large voltage pulse is applied to the pad (450). The gate-to-source voltage (Vgs) of the transistor (410) is reduced by the voltage drop across the inductor (412), which may improve the reliability of the transistor (410).
摘要翻译：描述了具有改进的ESD保护电路的放大器（例如，LNA）。在一个示例性设计中，放大器包括晶体管（410），电感器（412）和钳位电路（422）。晶体管（410）具有耦合到焊盘（450）的栅极并且为放大器提供信号放大。电感器（412）耦合到晶体管（410）的源极并为晶体管（410）提供源极变性。钳位电路（422）耦合在晶体管（410）的栅极和源极之间，并为晶体管（410）提供ESD保护。钳位电路（422）可以包括耦合在晶体管（410）的阵列和源极之间的至少一个二极管。钳位电路（422）通过电感器（412）传导电流，以便当对焊盘（450）施加大的电压脉冲时，产生电感器（412）两端的电压降。晶体管（410）的栅极 - 源极电压（Vgs）被电感器（412）上的电压降减小，这可以提高晶体管（410）的可靠性。

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