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1. 发明申请

WO2012018918A2 GENERATING A NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION 审中-公开
标题翻译：在具有第一磁性隧道接头和第二磁性隧道接头的位置处产生不可逆状态
公开(公告)号：WO2012018918A2
公开(公告)日：2012-02-09
申请号：PCT/US2011/046429
申请日：2011-08-03
申请人： QUALCOMM INCORPORATED , RAO, Hari, M. , KIM, Jung, Pill , KANG, Seung, H. , ZHU, Xiaochun , KIM, Tae, Hyun , LEE, Kangho , LI, Xia , HSU, Wah, Nam , HAO, Wuyang , SUH, Jungwon , YU, Nicholas, K. , NOWAK, Matthew, Michael , MILLENDORF, Steven, M. , ASHKENAZI, Asaf
发明人： RAO, Hari, M. , KIM, Jung, Pill , KANG, Seung, H. , ZHU, Xiaochun , KIM, Tae, Hyun , LEE, Kangho , LI, Xia , HSU, Wah, Nam , HAO, Wuyang , SUH, Jungwon , YU, Nicholas, K. , NOWAK, Matthew, Michael , MILLENDORF, Steven, M. , ASHKENAZI, Asaf
IPC分类号： G11C17/16
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

2. 发明申请

WO2012044640A1 RESISTANCE-BASED MEMORY HAVING TWO-DIODE ACCESS DEVICE 审中-公开
标题翻译：具有两个二极管访问器件的基于电阻的存储器
公开(公告)号：WO2012044640A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/053569
申请日：2011-09-28
申请人： QUALCOMM INCORPORATED , HAO, Wuyang , SUH, Jungwon , LEE, Kangho , KIM, Tae Hyun , KIM, Jung Pill , KANG, Seung H.
发明人： HAO, Wuyang , SUH, Jungwon , LEE, Kangho , KIM, Tae Hyun , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/003 , G11C2213/72 , G11C2213/74
摘要： A resistance -based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line (114) and a sense line (112) to generate a current through a resistance -based memory element (110) via a first diode (116) or a second diode (118). A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.
摘要翻译：基于电阻的存储器具有二极管接入装置。在特定实施例中，一种方法包括偏置位线（114）和感测线（112），以经由第一二极管（116）或第二二极管（118）产生通过基于电阻的存储元件（110）的电流，。第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。

3. 发明申请

WO2011119645A2 METHOD AND APPARATUS TO PROVIDE A CLOCK SIGNAL TO A CHARGE PUMP 审中-公开
标题翻译：向充电泵提供时钟信号的方法和装置
公开(公告)号：WO2011119645A2
公开(公告)日：2011-09-29
申请号：PCT/US2011/029481
申请日：2011-03-22
申请人： QUALCOMM Incorporated , HAO, Wuyang , KIM, Jung Pill , SUH, Jungwon
发明人： HAO, Wuyang , KIM, Jung Pill , SUH, Jungwon
IPC分类号： G06F17/50 , G05F3/02 , G06F1/10
CPC分类号： G06F1/06 , H02M3/07 , H02M3/073 , H02M2003/077
摘要： A method and apparatus for providing a clock signal to a charge pump is disclosed. In a particular embodiment, the method includes providing a first clock signal to a first charge pump unit of a charge pump. The method further includes providing a second clock signal to a second charge pump unit of the charge pump. A low-to-high transition of the first clock signal occurs substantially concurrently with a high-to-low transition of the second clock signal. Only one clock signal may be at a logic high voltage level at any given time.
摘要翻译：公开了一种用于向电荷泵提供时钟信号的方法和装置。在特定实施例中，该方法包括向电荷泵的第一电荷泵单元提供第一时钟信号。该方法还包括向电荷泵的第二电荷泵单元提供第二时钟信号。第一时钟信号的从低到高的跃迁与第二时钟信号的高到低的跃迁基本同时发生。在任何给定时间，只有一个时钟信号可能处于逻辑高电压电平。

4. 发明申请

WO2011143099A1 WRITE ENERGY CONSERVATION IN MEMORY 审中-公开
标题翻译：内存中的写入能量保存
公开(公告)号：WO2011143099A1
公开(公告)日：2011-11-17
申请号：PCT/US2011/035725
申请日：2011-05-09
申请人： QUALCOMM INCORPORATED , RAO, Hari M. , KIM, Jung Pill , KIM, Taehyun , ZHU, Xiaochun , LEE, Kangho , HAO, Wuyang
发明人： RAO, Hari M. , KIM, Jung Pill , KIM, Taehyun , ZHU, Xiaochun , LEE, Kangho , HAO, Wuyang
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1693
摘要： A method writes data to a resistive memory, such as spin torque transfer magnetic random access memory (STT-MRAM). The method writes received bits of data to a memory cell array, in response to a first write signal. The method also reads stored data from the memory cell array, after the first write signal is generated, and then compares the stored data with the received bits of data to determine whether each of the received bits of data was written to the memory. In response to a second write signal, received bits of data determined not to have been written during the first write signal, are written.
摘要翻译：一种方法将数据写入电阻性存储器，如自旋扭矩传递磁随机存取存储器（STT-MRAM）。该方法响应于第一写入信号将接收到的数据位写入存储单元阵列。该方法还在生成第一写信号之后从存储单元阵列中读取存储的数据，然后将所存储的数据与接收的数据位进行比较，以确定每个接收的数据位是否被写入存储器。响应于第二写入信号，写入在第一写入信号期间被确定为不被写入的数据的接收位。

5. 发明申请

WO2013019758A1 FAST MTJ SWITCHING WRITE CIRCUIT FOR MRAM ARRAY 审中-公开
标题翻译：用于MRAM阵列的快速MTJ切换写入电路
公开(公告)号：WO2013019758A1
公开(公告)日：2013-02-07
申请号：PCT/US2012/048905
申请日：2012-07-30
申请人： QUALCOMM Incorporated , LI, Xia , ZHU, Xiaochun , HAO, Wuyang
发明人： LI, Xia , ZHU, Xiaochun , HAO, Wuyang
IPC分类号： G11C11/16
CPC分类号： G11C11/1657 , G11C11/1659 , G11C11/1675
摘要： A transmission gate (110) is arranged between a current source (124) and a resistive memory element (108), a PMOS gate of the transmission gate has no source loading effect and a write current passes from the current source, and in a first direction through the resistive memory element, setting the resistive memory element to a magnetization state. An NMOS gate of the of the transmission gate has no source loading effect and another write current, passes through the resistive memory element, in a second direction opposite th first direction, and through the transmission gate, setting the resistive memory element to an opposite magnetization state.
摘要翻译：传输门（110）布置在电流源（124）和电阻存储元件（108）之间，传输门的PMOS栅极没有源负载效应，并且写入电流从电流源流过，而在第一方向通过电阻性存储元件，将电阻性存储元件设置为磁化状态。传输门的NMOS栅极没有源负载效应，另一写入电流在与第一方向相反的第二方向上通过电阻存储元件，并且通过传输门将电阻存储元件设置为相反的磁化州。

6. 发明申请

WO2013071269A2 LOW-POWER VOLTAGE REFERENCE CIRCUIT 审中-公开
标题翻译：低功耗电压参考电路
公开(公告)号：WO2013071269A2
公开(公告)日：2013-05-16
申请号：PCT/US2012/064725
申请日：2012-11-12
申请人： QUALCOMM INCORPORATED
发明人： HAO, Wuyang , SUH, Jungwon
IPC分类号： G05F3/24
CPC分类号： G05F3/242
摘要： Methods and apparatus for a providing temperature-compensated reference voltage are provided. In an example, a temperature-compensated voltage reference circuit includes a current mirror portion and a temperature-compensated output portion coupled to the current mirror portion. The temperature-compensated output portion comprises a very low threshold voltage (Vt) transistor coupled in series with a negative temperature coefficient transistor. The output portion can further include a positive temperature coefficient element coupled in series with the very low Vt transistor. The positive temperature coefficient element can be an adjustable resistive element. The output portion can further include an output transistor having a gate coupled to the current mirror portion and coupled between a supply voltage and the positive temperature coefficient element. The very low Vt transistor can be a substantially zero Vt n-channel metal-oxide-semiconductor (NMOS) transistor, and can be coupled in a diode configuration.
摘要翻译：提供了提供温度补偿参考电压的方法和装置。在一个示例中，温度补偿电压参考电路包括耦合到电流镜部分的电流镜部分和温度补偿输出部分。温度补偿输出部分包括与负温度系数晶体管串联耦合的非常低的阈值电压（Vt）晶体管。输出部分还可以包括与极低Vt晶体管串联耦合的正温度系数元件。正温度系数元件可以是可调电阻元件。输出部分还可以包括输出晶体管，其具有耦合到电流镜部分并且耦合在电源电压和正温度系数元件之间的栅极。非常低的Vt晶体管可以是基本为零的Vt n沟道金属氧化物半导体（NMOS）晶体管，并且可以以二极管配置耦合。

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