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1. 发明申请

WO2012018918A2 GENERATING A NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION 审中-公开
标题翻译：在具有第一磁性隧道接头和第二磁性隧道接头的位置处产生不可逆状态
公开(公告)号：WO2012018918A2
公开(公告)日：2012-02-09
申请号：PCT/US2011/046429
申请日：2011-08-03
申请人： QUALCOMM INCORPORATED , RAO, Hari, M. , KIM, Jung, Pill , KANG, Seung, H. , ZHU, Xiaochun , KIM, Tae, Hyun , LEE, Kangho , LI, Xia , HSU, Wah, Nam , HAO, Wuyang , SUH, Jungwon , YU, Nicholas, K. , NOWAK, Matthew, Michael , MILLENDORF, Steven, M. , ASHKENAZI, Asaf
发明人： RAO, Hari, M. , KIM, Jung, Pill , KANG, Seung, H. , ZHU, Xiaochun , KIM, Tae, Hyun , LEE, Kangho , LI, Xia , HSU, Wah, Nam , HAO, Wuyang , SUH, Jungwon , YU, Nicholas, K. , NOWAK, Matthew, Michael , MILLENDORF, Steven, M. , ASHKENAZI, Asaf
IPC分类号： G11C17/16
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

2. 发明申请

WO2011088359A1 MAGNETIC TUNNEL JUNCTION ON PLANARIZED ELECTRODE 审中-公开
标题翻译：平面电极上的磁性隧道结
公开(公告)号：WO2011088359A1
公开(公告)日：2011-07-21
申请号：PCT/US2011/021352
申请日：2011-01-14
申请人： QUALCOMM Incorporated , KANG, Seung, H. , LI, Xia , CHEN, Wei-Chuan , LEE, Kangho , ZHU, Xiaochun , HSU, Wah Nam
发明人： KANG, Seung, H. , LI, Xia , CHEN, Wei-Chuan , LEE, Kangho , ZHU, Xiaochun , HSU, Wah Nam
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01L43/08
摘要： A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers (126) are deposited on a bottom electrode (124) and are aligned with the bottom metal (122). An etch stop layer (302) may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer (202) may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ.
摘要翻译：具有直接接触的磁性隧道结（MTJ）被制造成具有较低的电阻，提高的产量和更简单的制造。较低的电阻提高了MTJ中的读取和写入过程。 MTJ层（126）沉积在底部电极（124）上并且与底部金属（122）对准。蚀刻停止层（302）可以沉积在底部金属附近，以防止围绕底部金属的绝缘体的过蚀刻。在沉积MTJ层之前将底部电极平坦化以提供基本平坦的表面。此外，可以在MTJ层之前的底部电极上沉积底层（202），以促进MTJ的期望特性。

3. 发明申请

WO2009131944A1 STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE AND INTEGRATION 审中-公开
标题翻译： STT MRAM磁铁隧道结构和集成
公开(公告)号：WO2009131944A1
公开(公告)日：2009-10-29
申请号：PCT/US2009/041132
申请日：2009-04-20
申请人： QUALCOMM INCORPORATED , KANG, Seung, H. , LI, Xia , GU, Shiqun , LEE, Kangho , ZHU, Xiaochun
发明人： KANG, Seung, H. , LI, Xia , GU, Shiqun , LEE, Kangho , ZHU, Xiaochun
IPC分类号： H01L43/08 , H01L27/22 , H01L43/12
CPC分类号： H01L27/222 , H01L43/08 , H01L43/12
摘要： A magnetic tunnel junction (MTJ) device (400) for a magnetic random access memory (MRAM) in a semiconductor back-end-of-line (BEOL) process flow includes a first metal interconnect (401) for communicating with at least one control device and a first electrode (406) for coupling to the first metal interconnect through a via formed in a dielectric passivation barrier (404) using a first mask. The device also includes an MTJ stack (407, 408, 409) for storing data coupled to the first electrode, a portion of the MTJ stack having lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode (410) is coupled to the MTJ stack and also has a same lateral dimension as defined by the second mask. The first electrode (406) and a portion (407) of the MTJ stack. are defined by a third mask. A second metal interconnect (415) is coupled to the second electrode and at least one other control device.
摘要翻译：用于半导体后端（BEOL）处理流程中的磁随机存取存储器（MRAM）的磁性隧道结（MTJ）装置（400）包括用于与至少一个控制器器件和第一电极（406），用于通过使用第一掩模在介电钝化屏障（404）中形成的通孔耦合到第一金属互连。该装置还包括用于存储耦合到第一电极的数据的MTJ堆叠（407,408,409），MTJ堆叠的一部分具有基于第二掩模的侧向尺寸。由第二掩模限定的部分在接触通孔之上。第二电极（410）耦合到MTJ堆叠并且还具有与第二掩模所限定的相同的横向尺寸。第一电极（406）和MTJ叠层的一部分（407）。由第三个掩码定义。第二金属互连（415）耦合到第二电极和至少一个其他控制装置。

4. 发明申请

WO2010101862A1 MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION 审中-公开
标题翻译：磁性隧道连接装置和制造
公开(公告)号：WO2010101862A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/025837
申请日：2010-03-02
申请人： QUALCOMM INCORPORATED , LEE, Kangho , ZHU, Xiaochun , LI, Xia , KANG, Seung, H.
发明人： LEE, Kangho , ZHU, Xiaochun , LI, Xia , KANG, Seung, H.
IPC分类号： H01L43/08 , H01L43/12 , H01F10/32
CPC分类号： H01L43/02 , B82Y25/00 , B82Y40/00 , G06F17/5068 , H01F10/3254 , H01F10/329 , H01F41/309 , H01F41/32 , H01L27/228 , H01L43/08 , H01L43/12
摘要： A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material (112) on a free layer (110) of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material.
摘要翻译：公开了一种磁性隧道接合装置及其制造方法。在一个具体实施方案中，该方法包括在磁性隧道结结构的自由层（110）上沉积封盖材料（112）以形成封盖层并氧化封盖材料的一部分以形成一层氧化材料。

5. 发明申请

WO2010101860A2 REDUCING SOURCE LOADING EFFECT IN SPIN TORQUE TRANSFER MAGNETORESITIVE RANDOM ACCESS MEMORY (STT-MRAM) 审中-公开
标题翻译：减小自旋转矩磁阻随机存取存储器（STT-MRAM）中的源负载效应
公开(公告)号：WO2010101860A2
公开(公告)日：2010-09-10
申请号：PCT/US2010/025834
申请日：2010-03-02
申请人： QUALCOMM INCORPORATED , LEE, Kangho , KANG, Seung, H. , ZHU, Xiaochun
发明人： LEE, Kangho , KANG, Seung, H. , ZHU, Xiaochun
IPC分类号： G11C11/16
CPC分类号： H01L43/08 , G06F17/5068 , G11C11/16 , G11C11/161 , G11C11/1675 , H01L43/02 , H01L43/12
摘要： Systems and methods to reduce source loading effects in STT-MRAM are disclosed. In a particular embodiment, a method includes determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell. The memory cell includes the MTJ structure serially coupled to an access transistor. The method also includes modifying an offset magnetic field that is incident to a free layer of the MTJ structure. The modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio.
摘要翻译：公开了用于减少STT-MRAM中的源加载效应的系统和方法。在特定实施例中，一种方法包括确定使得能够稳定操作存储器单元的磁隧道结（MTJ）结构的切换电流比。存储器单元包括串联耦合到存取晶体管的MTJ结构。该方法还包括修改入射到MTJ结构的自由层的偏移磁场。改进的偏移磁场使MTJ结构呈现开关电流比。

6. 发明申请

WO2010083233A1 MAGNETIC ELEMENT WITH STORAGE LAYER MATERIALS 审中-公开
标题翻译：具有储存层材料的磁性元件
公开(公告)号：WO2010083233A1
公开(公告)日：2010-07-22
申请号：PCT/US2010/020919
申请日：2010-01-13
申请人： QUALCOMM INCORPORATED , ZHU, Xiaochun , LI, Xia , KANG, Seung, H.
发明人： ZHU, Xiaochun , LI, Xia , KANG, Seung, H.
IPC分类号： H01L43/10 , G11C11/15
CPC分类号： H01L43/10 , G11C11/161 , H01L43/12
摘要： According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.
摘要翻译：根据本发明的实施例，磁性隧道结（MTJ）元件包括参考铁磁层，存储铁磁层和绝缘层。存储铁磁层包括通过非磁性子层耦合到CoFe子层和/或NiFe子层的CoFeB子层。绝缘层设置在参考和存储铁磁层之间。

7. 发明申请

WO2010002632A1 SYSTEM AND METHOD TO FABRICATE MAGNETIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：制造磁性随机存取存储器的系统和方法
公开(公告)号：WO2010002632A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/048248
申请日：2009-06-23
申请人： QUALCOMM INCORPORATED , LI, Xia , ZHU, Xiaochun , KANG, Seung, H.
发明人： LI, Xia , ZHU, Xiaochun , KANG, Seung, H.
IPC分类号： H01L43/08 , H01L43/12 , C23C14/35 , H01F41/18 , H01J37/34
CPC分类号： H01L43/08 , B82Y25/00 , B82Y40/00 , G11C11/16 , H01F41/307 , H01L43/12
摘要： A system and method to fabricate magnetic random access memory is disclosed. In particular, a method of aligning a magnetic film during deposition is disclosed. The method includes applying a first magnetic field along a first direction (130) in a region in which a substrate resides during a deposition of a first magnetic material onto the substrate. The method further includes applying a second magnetic field (132) along a second direction in the region during the deposition of the first magnetic material onto the substrate.
摘要翻译：公开了制造磁随机存取存储器的系统和方法。特别地，公开了一种在沉积期间对准磁性膜的方法。该方法包括在将第一磁性材料沉积到衬底上的过程中沿着第一方向（130）施加第一磁场。该方法还包括在将第一磁性材料沉积到衬底上的同时沿该区域中的第二方向施加第二磁场（132）。

8. 发明申请

WO2013040072A1 STRAIN INDUCED REDUCTION OF SWITCHING CURRENT IN SPINTRANSFER TORQUE SWITCHING DEVICES 审中-公开
标题翻译：螺旋转矩开关装置中开关电流的应变诱导减小
公开(公告)号：WO2013040072A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/054915
申请日：2012-09-12
申请人： QUALCOMM INCORPORATED , ZHU, Xiaochun , LI, Xia , CHEN, Wei-Chuan , KANG, Seung, H.
发明人： ZHU, Xiaochun , LI, Xia , CHEN, Wei-Chuan , KANG, Seung, H.
IPC分类号： H01L43/08 , G11C11/16
CPC分类号： H01L43/12 , G11C11/16 , G11C11/161 , G11C11/1675 , H01F10/3254 , H01F10/3286 , H01F41/325 , H01L27/222 , H01L41/12 , H01L43/08 , H01L43/10
摘要： Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ (202) to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction (236, 234) and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress (228) and permanently includes the directed static strain/strain that provides reduced switching current.
摘要翻译：使用在MTJ（202）上引起定向静态应变/应力以增加垂直磁各向异性的工艺和结构构造来构造部分垂直磁各向异性（PPMA）型磁性随机存取存储器单元。因此，MTJ的开关电流降低。在制造过程中，在受控方向（236,234）和/或受控的幅度下诱导MTJ上的定向静态应变/应力。 MTJ永久地受到预定的定向应力（228），并且永久地包括提供减小的开关电流的定向静态应变/应变。

9. 发明申请

WO2010088669A1 MAGNETIC TUNNEL JUNCTION COMPRISING A TUNNEL BARRIER, PINNED LAYER AND TOP ELECTRODE FORMED IN A DAMASCENE-TYPE PROCESS 审中-公开
标题翻译：包含隧道式障碍物，密封层和形成大型过程的顶部电极的磁隧道结
公开(公告)号：WO2010088669A1
公开(公告)日：2010-08-05
申请号：PCT/US2010/022887
申请日：2010-02-02
申请人： QUALCOMM INCORPORATED , GU, Shiqun , KANG, Seung, H. , ZHU, Xiaochun
发明人： GU, Shiqun , KANG, Seung, H. , ZHU, Xiaochun
IPC分类号： H01L27/22 , H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01L27/222 , H01L27/228 , H01L27/24 , H01L29/82 , H01L43/08
摘要： A magnetic tunnel junction storage element for a spin transfer torque magnetoresistive random access memory (STT-MRAM) bit cell includes a bottom electrode layer, (150) a pinned layer (160) adjacent to the bottom electrode layer, a dielectric layer (70) encapsulating a portion of the bottom electrode layer and the pinned layer, the dielectric layer including sidewalls that define a hole adjacent to a portion of the pinned layer, a tunneling barrier (190) adjacent to the pinned layer, a free layer (200) adjacent to the tunneling barrier, and a top electrode (210) adjacent to the free layer, wherein a width of the bottom electrode layer and/or the pinned barrier in a first direction is greater than a width of a contact area between the pinned layer and the tunneling barrier in the first direction. Also a method of forming an STT-MRAM bit cell is disclosed.
摘要翻译：用于自旋转移磁阻随机存取存储器（STT-MRAM）位单元的磁性隧道结存储元件包括底部电极层，（150）邻近底部电极层的钉扎层（160），介电层（70）封装底部电极层和钉扎层的一部分，电介质层包括限定与被钉扎层的一部分相邻的孔的侧壁，邻近被钉扎层的隧道势垒（190），邻近的自由层（200）和与所述自由层相邻的顶部电极（210），其中所述底部电极层和/或所述被钉扎的屏障在第一方向上的宽度大于所述被钉扎层和所述被钉扎层之间的接触面积的宽度隧道屏障在第一个方向。还公开了一种形成STT-MRAM位单元的方法。

10. 发明申请

WO2009131890A1 METHOD OF FORMING A MAGNETIC TUNNEL JUNCTION USING A SINGLE MASK 审中-公开
标题翻译：使用单个掩模形成磁性隧道连接的方法
公开(公告)号：WO2009131890A1
公开(公告)日：2009-10-29
申请号：PCT/US2009/040823
申请日：2009-04-16
申请人： QUALCOMM INCORPORATED , KANG, Seung, H. , BANG, David , LEE, Kangho
发明人： KANG, Seung, H. , BANG, David , LEE, Kangho
IPC分类号： H01L27/22 , H01L43/08 , H01L43/12
CPC分类号： H01L43/02 , G11C11/16 , G11C11/161 , H01L27/228 , H01L43/08 , H01L43/12
摘要： .A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer (36) and at least a first metal interconnect (37). Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction materxal layers (2, 32, 12, 11, 6) are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.
摘要翻译：一种用于将磁性隧道结（MTJ）器件集成到集成电路中的方法包括在半导体后端（BEOL）工艺流程中提供具有第一层间介电层（36）和至少第一金属互连（37）。在第一层间介电层和第一金属互连之后，沉积磁隧道结材料层（2,32,12,11,6）。从材料层，使用单个掩模工艺来限定耦合到第一金属互连的磁性隧道结叠层。磁性隧道结堆叠集成在集成电路中。

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