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1. 发明申请

WO2018151956A1 DIE-TO-DIE INTERFACE CONFIGURATION AND METHODS OF USE THEREOF 审中-公开
公开(公告)号：WO2018151956A1
公开(公告)日：2018-08-23
申请号：PCT/US2018/016730
申请日：2018-02-02
申请人： QUALCOMM INCORPORATED
发明人： DUBOWSKI, Kenneth , PETERSON, Luverne Ray , BRYAN, Thomas , KNOL, Stephen , DUNDIGAL, Sreeker , LOKE, Alvin Leng Sun
IPC分类号： H03K19/0175
摘要： A semiconductor die including: a die-to-die interface including an input /output (I/O) circuitry area and an electrical contact area; wherein the electrical contact area includes an array of electrical contacts disposed on a side of the semiconductor die; and wherein the I/O circuitry area includes a plurality of drivers, each of the drivers coupled to at least one electrical contact in the electrical contact area, and a plurality of electrostatic discharge (ESD) protection devices, each of the ESD protection devices coupled to a respective driver, further wherein the I/O circuitry area and the electrical contact area are separated in a top-down view of the semiconductor die.

2. 发明申请

WO2019190697A1 CO-PLACEMENT OF RESISTOR AND OTHER DEVICES TO IMPROVE AREA & PERFORMANCE 审中-公开
公开(公告)号：WO2019190697A1
公开(公告)日：2019-10-03
申请号：PCT/US2019/020184
申请日：2019-03-01
申请人： QUALCOMM INCORPORATED
发明人： WEE, Tin Tin , LOKE, Alvin Leng Sun , SCHNEIDER, Jacob
IPC分类号： H01L27/02 , H01L23/522 , H01L49/02
摘要： Co-placement of resistor and other devices to improve area and performance is disclosed. In one implementation, a semiconductor circuit includes a resistor residing on a back end of line (BEOL) resistor layer, a plurality of interlevel metal vias coupling the BEOL resistor layer to one or more metal layers underneath the BEOL resistor layer, and a diode residing on a silicon substrate underneath the one or more metal layers, wherein a planar surface of the diode and a planar surface of the resistor at least partially overlap with each other, and the diode and the resistor are coupled to each other through the plurality of interlevel metal vias.

3. 发明申请

WO2016160294A1 PROGRAMMABLE HIGH-SPEED EQUALIZER AND RELATED METHOD 审中-公开
标题翻译：可编程高速均衡器及相关方法
公开(公告)号：WO2016160294A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/021617
申请日：2016-03-09
申请人： QUALCOMM INCORPORATED
发明人： MIZANUR RAHMAN, Mohammed , SCHNEIDER, Jacob Stephen , BRYAN, Thomas Clark , PETERSON, LuVerne Ray , LYNCH, Gregory Francis , LOKE, Alvin Leng Sun
IPC分类号： H04L25/03 , H04L25/02 , H03F3/45
CPC分类号： H03K17/687 , H03F3/45197 , H03F2203/45488 , H03F2203/45494 , H03F2203/45504 , H04L25/0272 , H04L25/0292 , H04L25/03878
摘要： A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.
摘要翻译：提供了一种可编程均衡器及相关方法。均衡器包括分别与第一电压轨（Vdd）和第二电压轨（地）之间的一对输入FET和一对负载电阻串联耦合的一对电流设定场效应晶体管（FET）。可编程均衡电路耦合在输入FET的源极之间，包括多个可选择的电阻路径和可变电容器，其也可以被配置为多个可选择的电容路径。每个可选择的电阻路径（以及每个可选择的电容路径）包括用于选择性地耦合在输入FET的源极之间的对应的电阻（或电容）路径的选择FET。在其中一个输入FET被参考栅极电压偏置的情况下，每个选择FET的源极耦合到这种输入FET的源极。

4. 发明申请

WO2016060780A1 SYSTEMS AND METHODS FOR PROVIDING DATA CHANNELS AT A DIE-TO-DIE INTERFACE 审中-公开
标题翻译：用于在模 - 死接口中提供数据通道的系统和方法
公开(公告)号：WO2016060780A1
公开(公告)日：2016-04-21
申请号：PCT/US2015/050596
申请日：2015-09-17
申请人： QUALCOMM INCORPORATED
发明人： PETERSON, LuVerne Ray , BRYAN, Thomas Clark , LOKE, Alvin Leng Sun , WEE, Tin Tin , LYNCH, Gregory Francis , KNOL, Stephen Robert
IPC分类号： G06F1/10 , G06F17/50 , G11C7/22
CPC分类号： H01L25/065 , G06F1/10 , G06F17/5072 , G06F2217/62 , G06F2217/78 , H01L2924/0002 , H04L7/0095 , H01L2924/00
摘要： A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.
摘要翻译：一种电路包括具有暴露的数据节点的第一阵列的第一裸片和具有暴露的数据节点的第二阵列的第二裸片，其中第一阵列的给定数据节点对应于相应的数据其中所述第一阵列和所述第二阵列共享所述数据节点的空间布置，其中所述第一裸片具有数据输入和用于所述第一阵列的第一侧上的所述第一阵列的每个数据节点的时序逻辑电路，第一阵列，并且其中第二管芯具有用于第二阵列的第二侧上的第二阵列的每个数据节点的数据输出和时序逻辑电路，第一和第二侧不同。

5. 发明申请

WO2016014186A1 SYSTEMS AND METHODS FOR WAFER-LEVEL LOOPBACK TEST 审中-公开
标题翻译：用于水平回波测试的系统和方法
公开(公告)号：WO2016014186A1
公开(公告)日：2016-01-28
申请号：PCT/US2015/036743
申请日：2015-06-19
申请人： QUALCOMM INCORPORATED
发明人： LOKE, Alvin Leng Sun , BRYAN, Thomas Clark , JALILIZEINALI, Reza , WEE, Tin Tin , KNOL, Stephen Robert , PETERSON, LuVerne Ray
IPC分类号： G01R31/3185 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31716 , G01R31/318513
摘要： Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.
摘要翻译：提供了用于环回测试的电路和方法。一个管芯将每个发射器（TX）的接收器（RX）以及每个接收器的TX都包含在内。该架构被应用于每个位，因此，例如，在操作期间发送或接收32个数据位的管芯将具有32个收发器（每个位一个）。专注于收发器之一，环回架构包括TX数据路径和RX数据路径，其通过诸如收发器之间的通孔的外部接点相互耦合。芯片还包括馈送TX数据路径的发射时钟树和馈送RX数据路径的接收时钟树。传输时钟树通过露出在芯片表面上的导电时钟节点馈送接收时钟树。一些系统还包括时钟路径中的可变延迟。

6. 发明申请

WO2020190467A1 THIN-FILM RESISTORS WITH FLEXIBLE TERMINAL PLACEMENT FOR AREA SAVING 审中-公开
公开(公告)号：WO2020190467A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/019841
申请日：2020-02-26
申请人： QUALCOMM INCORPORATED
发明人： CHINTARLAPALLI REDDY, Harikrishna , LOKE, Alvin Leng Sun
IPC分类号： H01L27/01 , H01L49/02 , H01C1/14 , H01L27/08
摘要： An apparatus including a dielectric layer; and a set of thin-film resistors arranged in a row extending in a first direction on the dielectric layer, wherein lengths of the set of thin-film resistors in a second direction substantially orthogonal to the first direction are substantially the same, wherein the set of thin-film resistors includes a first subset of one or more thin-film resistors with respective terminals spaced apart by a first distance, and wherein the set of thin-film resistors includes a second subset of one or more thin-film resistors with respective terminals spaced apart by a second distance, the first distance being different than the second distance.

7. 发明申请

WO2016160329A1 CIRCUITS AND METHODS PROVIDING HIGH-SPEED DATA LINK WITH EQUALIZER 审中-公开
标题翻译：提供均衡器的高速数据链路的电路和方法
公开(公告)号：WO2016160329A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/022508
申请日：2016-03-15
申请人： QUALCOMM INCORPORATED
发明人： RAHMAN, Mohammed Mizanur , BRYAN, Thomas Clark , SCHNEIDER, Jacob Stephen , PETERSON, LuVerne Ray , WEE, Tin Tin , LOKE, Alvin Leng Sun
IPC分类号： H04L25/02 , H04L25/03
CPC分类号： H04L25/03885 , H04B1/16 , H04L25/0278 , H04L25/029 , H04L25/0292 , H04L25/0298 , H04L25/03 , H04L25/03834 , H04L25/03878 , H04L25/08
摘要： Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but-for the equalizer.
摘要翻译：公开了用于使用失配的阻抗和均衡器来提供接收和捕获数据以节省功率的方法，系统和电路。与传输线通信的数据接收机，数据接收机具有相对于传输线的特性阻抗失配的终端阻抗; 以及与数据接收器通信的均衡器，所述均衡器被配置为从数据接收器接收信道发送的数据信号并且重新形成信号以减小失真RC衰减; 其中所述电路被配置为可选择地以第一模式操作，其中所述终端阻抗相对于所述传输线的所述特性阻抗匹配，以及第二模式，其中所述终端阻抗相对于所述传输线的特征阻抗不匹配，信号不可恢复，但是对于均衡器。

8. 发明申请

WO2016153778A1 DRIVER USING PULL-UP NMOS TRANSISTOR 审中-公开
标题翻译：驱动器使用拉高NMOS晶体管
公开(公告)号：WO2016153778A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/021397
申请日：2016-03-08
申请人： QUALCOMM INCORPORATED
发明人： THILENIUS, Stephen Clifford , ISAKANIAN, Patrick , LOKE, Alvin Leng Sun , BRYAN, Thomas Clark , PETERSON, LuVerne Ray
IPC分类号： H03K19/0185 , G11C7/10
CPC分类号： H03K19/017518 , G11C7/1057 , H03K5/14 , H03K19/018507
摘要： In one embodiment, a system comprises a pre-driver circuit and a driver. The pre-driver circuit is powered by a first supply voltage, and configured to output a pre-drive signal. The driver comprises a pull-up NMOS transistor having a drain coupled to a second supply voltage, and a source coupled to an output of the driver, wherein the second supply voltage is lower than the first supply voltage by at least a threshold voltage of the pull-up NMOS transistor. The driver also comprises a drive circuit coupled to a gate of the pull-up NMOS transistor, wherein the drive circuit is configured to receive the pre-drive signal and to drive the gate of the pull-up NMOS transistor with a voltage approximately equal to the first supply voltage to drive the output of the driver to a high state depending on a logic state of the pre-drive signal.
摘要翻译：在一个实施例中，系统包括预驱动器电路和驱动器。预驱动器电路由第一电源电压供电，并且被配置为输出预驱动信号。驱动器包括具有耦合到第二电源电压的漏极的上拉NMOS晶体管和耦合到驱动器的输出的源，其中第二电源电压低于第一电源电压至少一个阈值电压上拉式NMOS晶体管。驱动器还包括耦合到上拉NMOS晶体管的栅极的驱动电路，其中驱动电路被配置为接收预驱动信号并且驱动上拉NMOS晶体管的栅极，其电压近似等于根据预驱动信号的逻辑状态，第一电源电压将驱动器的输出驱动到高电平状态。

9. 发明申请

WO2016144482A1 TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM 审中-公开
标题翻译：晶闸管配置为栅极过渡和电路
公开(公告)号：WO2016144482A1
公开(公告)日：2016-09-15
申请号：PCT/US2016/017733
申请日：2016-02-12
申请人： QUALCOMM INCORPORATED
发明人： LOKE, Alvin Leng Sun , YU, Bo , THILENIUS, Steven Clifford , JALILIZEINALI, Reza , ISAKANIAN, Patrick
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K17/0822 , H03K19/00315 , H03K19/018521
摘要： An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.
摘要翻译：提供电子电路和操作电子电路的方法。电子电路包括用于将输出电路的输入/输出（I / O）节点提升到第一电压的上拉晶体管和用于将上拉晶体管耦合到I / O节点的第一隔离晶体管。电子电路还包括用于将I / O节点下拉到第二电压的下拉晶体管和用于将下拉晶体管耦合到I / O节点的第二隔离晶体管。在电子电路中，上拉和下拉晶体管是支持第一漏极 - 源极电压和第一栅极 - 源极电压的晶体管，而第一和第二隔离晶体管是支撑第一漏极并且第二栅极至源极电压大于第一栅极至源极电压。

10. 发明申请

WO2016010632A1 SYSTEMS AND METHODS FOR CLOCK DISTRIBUTION IN A DIE-TO-DIE INTERFACE 审中-公开
标题翻译：在DIE-DIE接口中的时钟分配的系统和方法
公开(公告)号：WO2016010632A1
公开(公告)日：2016-01-21
申请号：PCT/US2015/032458
申请日：2015-05-26
申请人： QUALCOMM INCORPORATED
发明人： BRYAN, Thomas Clark , LOKE, Alvin Leng Sun , KNOL, Stephen , LYNCH, Gregory Francis , WEE, Tin Tin , PETERSON, LuVerne Ray , LI, Yue
IPC分类号： G06F1/10 , G11C7/22 , H01L25/065 , H01L23/538
CPC分类号： H03K5/15013 , G06F1/10 , G11C7/22 , H01L23/5384 , H01L23/5389 , H01L25/0655 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/24137 , H01L2224/73267 , H01L2924/15311
摘要： Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.
摘要翻译：提供了芯片到芯片时钟分配的电路。系统包括第一管芯上的传输时钟树和第二管芯上的接收时钟树。传输时钟树和接收时钟树是相同的或非常接近相同的，所以发送时钟树上的给定位的插入延迟与对应于该时钟树上的给定位的位的插入延迟相同接收时钟树。虽然在同一个时钟树中可能存在从位到位的时钟偏差，但是不同芯片上的相应位具有相同的时钟插入延迟。

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