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1. 发明申请

WO2014033351A1 DISCOVERY METHOD AND APPARATUSES AND SYSTEM FOR DISCOVERY 审中-公开
标题翻译：发现方法和发现的方法和系统
公开(公告)号：WO2014033351A1
公开(公告)日：2014-03-06
申请号：PCT/FI2012/050819
申请日：2012-08-28
申请人： NOKIA CORPORATION , KUUSILINNA, Kimmo , AALTONEN, Timo , LEPPÄNEN, Tapani , PALIN, Arto
发明人： KUUSILINNA, Kimmo , AALTONEN, Timo , LEPPÄNEN, Tapani , PALIN, Arto
IPC分类号： H04W8/00 , H04W84/18 , H04W52/00
CPC分类号： H04W8/005 , H04W52/0209 , H04W52/0261 , H04W76/14 , H04W84/12 , Y02D70/142 , Y02D70/144 , Y02D70/164 , Y02D70/166
摘要： The invention relates to methods, apparatuses, systems and computer program products for discovery of nearby devices (510, 520, 525, 540, 545). To facilitate discovery of nearby, i.e. proximal, devices, a discovery control signal (570, 572, 574, 576, 578) from a control device (530) may be used to control the discovery, e.g. how or when the discovery is carried out. The devices may send status information of their status to be used by the control device or the control system for forming the discovery control signal. The control device, e.g. a server, may form the discovery control signal based on this status information. Discovery of proximal devices may then be carried out based on the received discovery control signal.
摘要翻译：本发明涉及用于发现附近设备（510,520,525,540,545）的方法，设备，系统和计算机程序产品。为了便于发现附近，即近端设备，可以使用来自控制设备（530）的发现控制信号（570,572,574,576,578）来控制发现，例如，如何或何时进行发现。设备可以发送其状态的状态信息以由控制设备或用于形成发现控制信号的控制系统使用。控制装置，例如服务器可以基于该状态信息形成发现控制信号。然后可以基于接收到的发现控制信号来执行近端设备的发现。

2. 发明申请

WO2014033350A1 DISCOVERY METHOD AND APPARATUSES AND SYSTEM FOR DISCOVERY 审中-公开
标题翻译：发现方法和发现的方法和系统
公开(公告)号：WO2014033350A1
公开(公告)日：2014-03-06
申请号：PCT/FI2012/050818
申请日：2012-08-28
申请人： NOKIA CORPORATION , KUUSILINNA, Kimmo , AALTONEN, Timo , LEPPÄNEN, Tapani
发明人： KUUSILINNA, Kimmo , AALTONEN, Timo , LEPPÄNEN, Tapani
IPC分类号： H04W8/00 , H04L29/08 , H04W84/18
CPC分类号： H04W8/005 , H04W4/023 , H04W4/029 , H04W4/21 , H04W8/22 , H04W40/246 , H04W64/003 , H04W84/18
摘要： The invention relates to methods, apparatuses, systems and computer program products for discovery of nearby devices. To facilitate discovery of nearby, i.e. proximal, devices, after receiving a trigger signal (110), that is, a signal related to a user action, proximity of other devices is determined and a proximity fingerprint is formed from this information (120), for example to be stored in a fingerprint database (130). When a change in proximity information of a device is detected, proximity fingerprints are accessed and the fingerprints are searched for in the current proximity information of the user device. In this manner, the user may be alerted or programs (or the system) may be controlled when a stored proximity fingerprint is detected in the current set of nearby devices.
摘要翻译：本发明涉及用于发现附近装置的方法，装置，系统和计算机程序产品。为了便于发现附近的设备，即在接收到触发信号（110）之后，即与用户动作有关的信号，确定其他设备的接近度，并且从该信息（120）形成接近指纹，例如存储在指纹数据库（130）中。当检测到设备的邻近信息的改变时，接近指纹被访问，并且在用户设备的当前邻近信息中搜索指纹。以这种方式，当在当前的一组附近设备中检测到存储的接近指纹时，可以警告用户或程序（或系统）。

3. 发明申请

WO2007118619A2 IMPROVEMENTS IN OR RELATING TO IMAGE PROJECTING 审中-公开
标题翻译：改进或相关图像投影
公开(公告)号：WO2007118619A2
公开(公告)日：2007-10-25
申请号：PCT/EP2007/003079
申请日：2007-04-04
申请人： NOKIA CORPORATION , LEPPÄNEN, Tapani , PESONEN, Mika , KUUSILINNA, Kimmo , LAUNIAINEN, Aki , SOKEILA, Tomi
发明人： LEPPÄNEN, Tapani , PESONEN, Mika , KUUSILINNA, Kimmo , LAUNIAINEN, Aki , SOKEILA, Tomi
IPC分类号： G03B21/26 , G03B21/60
CPC分类号： H04N9/3185 , G03B21/26
摘要： A projector screen is shown comprising one or more markers arranged to be used by projection processing circuitry to calculate a user perceived distortion in an image to be projected on the projector screen. A related method, computer program and projection processing circuitry are also shown.
摘要翻译：显示投影仪屏幕，其包括布置成由投影处理电路使用的一个或多个标记，以计算要投影在投影仪屏幕上的图像中的用户感觉到的失真。还示出了相关方法，计算机程序和投影处理电路。

4. 发明申请

WO2011095678A1 UPDATE HANDLER FOR MULTI-CHANNEL CACHE 审中-公开
标题翻译：用于多通道高速缓存的更新操作
公开(公告)号：WO2011095678A1
公开(公告)日：2011-08-11
申请号：PCT/FI2011/050053
申请日：2011-01-25
申请人： NOKIA CORPORATION , AHO, Eero , NIKARA, Jari , KUUSILINNA, Kimmo
发明人： AHO, Eero , NIKARA, Jari , KUUSILINNA, Kimmo
IPC分类号： G06F12/08 , G06F12/10 , G06F11/10
CPC分类号： G06F12/0844 , G06F12/084 , G06F12/0846 , G06F12/0851 , G06F12/0859 , G06F12/0862 , G06F2212/1016 , G06F2212/601 , G06F2212/6042
摘要： Disclosed herein is a miss handler for a multi-channel cache memory, and a method that includes determining a need to update a multi-channel cache memory due at least to one of an occurrence of a cache miss or a data prefetch being needed. The method further includes operating a multi-channel cache miss handler to update at least one cache channel storage of the multi-channel cache memory from a main memory.
摘要翻译：本文公开了一种用于多通道高速缓冲存储器的未命中处理器，以及一种方法，其包括至少由于存在高速缓存未命中的发生或需要的数据预取而导致更新多通道高速缓冲存储器的需要。该方法还包括操作多通道高速缓存未命中处理程序以从主存储器更新多通道高速缓冲存储器的至少一个高速缓存通道存储器。

5. 发明申请

WO2011095677A1 CHANNEL CONTROLLER FOR MULTI-CHANNEL CACHE 审中-公开
标题翻译：多通道高速缓存的通道控制器
公开(公告)号：WO2011095677A1
公开(公告)日：2011-08-11
申请号：PCT/FI2011/050052
申请日：2011-01-25
申请人： NOKIA CORPORATION , NIKARA, Jari , AHO, Eero , KUUSILINNA, Kimmo
发明人： NIKARA, Jari , AHO, Eero , KUUSILINNA, Kimmo
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0864 , G06F12/084 , G06F12/0851 , G06F12/0893 , G06F12/1036 , G06F2212/1028 , G06F2212/1048 , G06F2212/301 , G06F2212/601 , G06F2212/6042 , Y02D10/13
摘要： Disclosed herein is a channel controller for a multi-channel cache memory, and a method that includes receiving a memory address associated with a memory access request to a main memory of a data processing system; translating the memory address to form a first access portion identifying at least one partition of a multi-channel cache memory, and at least one further access portion, where the at least one partition includes at least one channel; and applying the at least one further access portion to the at least one channel of the multi-channel cache memory.
摘要翻译：本文公开了一种用于多通道高速缓冲存储器的通道控制器，以及一种方法，其包括将与存储器访问请求相关联的存储器地址接收到数据处理系统的主存储器; 翻译存储器地址以形成识别多通道高速缓冲存储器的至少一个分区的第一访问部分和至少一个另外的访问部分，其中所述至少一个分区包括至少一个信道; 以及将所述至少一个另外的访问部分应用于所述多通道高速缓冲存储器的所述至少一个通道。

6. 发明申请

WO2008119732A1 A MODULAR DEVICE COMPONENT 审中-公开
标题翻译：模块化器件组件
公开(公告)号：WO2008119732A1
公开(公告)日：2008-10-09
申请号：PCT/EP2008/053630
申请日：2008-03-27
申请人： NOKIA CORPORATION , KUUSILINNA, Kimmo , NIKARA, Jari , LIUHA, Petri
发明人： KUUSILINNA, Kimmo , NIKARA, Jari , LIUHA, Petri
IPC分类号： G06F15/17
CPC分类号： H04L69/12 , H04L47/125 , H04L47/726 , H04L49/90 , H04L49/9063 , H04L67/1002 , H04L67/1006 , H04L69/26
摘要： A component (23) of an electronic device comprises a network connection processor (27), which comprises a physical network connection block (31) to receive data from and transmit data to a network and a first data processor (27) configured to process data arriving at the network connection processor (27), and a second data processor (28) configured to process data received from the network connection processor (27).
摘要翻译：电子设备的组件（23）包括网络连接处理器（27），网络连接处理器（27）包括物理网络连接块（31），用于从网络接收数据并向网络发送数据;以及第一数据处理器（27），被配置为处理数据到达网络连接处理器（27），以及第二数据处理器（28），被配置为处理从网络连接处理器（27）接收的数据。

7. 发明申请

WO2011032593A1 MULTI-CHANNEL CACHE MEMORY 审中-公开
标题翻译：多通道高速缓存存储器
公开(公告)号：WO2011032593A1
公开(公告)日：2011-03-24
申请号：PCT/EP2009/062076
申请日：2009-09-17
申请人： NOKIA CORPORATION , NIKARA, Jari , AHO, Eero , KUUSILINNA, Kimmo
发明人： NIKARA, Jari , AHO, Eero , KUUSILINNA, Kimmo
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/084 , G06F12/0842 , G06F12/0844
摘要： A cache memory including:a plurality of parallel input ports configured to receive, in parallel, memory access requests wherein each parallel input port is operable to receive a memory access request for any one of a plurality of processing units; and a plurality of cache blocks wherein each cache block is configured to receive memory access requests from a unique one of the plurality of input ports such that there is a one-to-one mapping between the plurality of parallel input ports and the plurality of cache blocks and wherein each of the plurality of cache blocks is configured to serve a unique portion of an address space of the memory.
摘要翻译：一种高速缓冲存储器，包括：多个并行输入端口，被配置为并行地接收存储器访问请求，其中每个并行输入端口可操作以接收多个处理单元中的任何一个的存储器访问请求; 以及多个高速缓存块，其中每个高速缓存块被配置为从所述多个输入端口中的唯一的输入端口接收存储器访问请求，使得在所述多个并行输入端口和所述多个高速缓存器之间存在一对一映射块，并且其中所述多个高速缓存块中的每一个被配置为服务于所述存储器的地址空间的唯一部分。

8. 发明申请

WO2008041069A3 3D CHIP ARRANGEMENT INCLUDING MEMORY MANAGER 审中-公开
公开(公告)号：WO2008041069A3
公开(公告)日：2008-04-10
申请号：PCT/IB2007/001818
申请日：2007-07-02
申请人： NOKIA CORPORATION , LAHTINEN, Vesa , HILL, Tapio , KUUSILINNA, Kimmo , NIKARA, Jari , KUULUSA, Mika , MÄKELÄINEN, Tommi
发明人： LAHTINEN, Vesa , HILL, Tapio , KUUSILINNA, Kimmo , NIKARA, Jari , KUULUSA, Mika , MÄKELÄINEN, Tommi
IPC分类号： G11C5/02 , H01L23/528
摘要： Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.

9. 发明申请

WO2008041070A1 REALLOCATION OF MEMORY THROUGH GLOBAL ADDRESSING 审中-公开
标题翻译：通过全球化解决重读记忆
公开(公告)号：WO2008041070A1
公开(公告)日：2008-04-10
申请号：PCT/IB2007/001824
申请日：2007-07-03
申请人： NOKIA CORPORATION , LAHTINEN, Vesa , KUUSILINNA, Kimmo , NIKARA, Jari , NURMINEN, Jukka, M.
发明人： LAHTINEN, Vesa , KUUSILINNA, Kimmo , NIKARA, Jari , NURMINEN, Jukka, M.
IPC分类号： G06F12/06
CPC分类号： G06F12/0284 , G06F12/0653 , G06F2212/205 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Systems, apparatuses and methods for efficient logical memory management using centralized memory management. One embodiment involves allocating a first memory region to a first subsystem, generating a region code associated with the allocated memory region, storing the region code in connection with an address of the memory region, and defining the first subsystem as a first owner for the memory region by storing a unique subsystem identifier together with the region code in a parameter table. In this manner, a memory region may be globally addressed by its region code and an ownership to a subsystem is defined and stored.
摘要翻译：使用集中式内存管理的高效逻辑内存管理的系统，设备和方法。一个实施例涉及将第一存储器区域分配给第一子系统，生成与分配的存储器区域相关联的区域代码，存储与存储器区域的地址有关的区域代码，以及将第一子系统定义为存储器的第一所有者通过在参数表中存储唯一的子系统标识符和区域代码。以这种方式，可以通过其区域代码对存储器区域进行全局寻址，并且定义并存储对子系统的所有权。

10. 发明申请

WO2002101996A1 METHOD FOR ADAPTING A BUS AND A BUS 审中-公开
标题翻译：适应总线和总线的方法
公开(公告)号：WO2002101996A1
公开(公告)日：2002-12-19
申请号：PCT/FI2002/000497
申请日：2002-06-07
申请人： NOKIA CORPORATION , PARVIAINEN, Jari , HÄMÄLÄINEN, Timo , KUUSILINNA, Kimmo
发明人： PARVIAINEN, Jari , HÄMÄLÄINEN, Timo , KUUSILINNA, Kimmo
IPC分类号： H04L12/40
CPC分类号： H04L12/10 , H04L12/407 , H04L12/44 , H04L12/4625
摘要： A method for adapting a bus to data traffic in a system comprising several functional units (311, 312, , 31n) and a bus structure. The functional units are divided into at least two sets so that units, which mainly transfer data with each other belong to a same set and are interfaced with the same separate sub-bus (321; 322). The sub-buses can be united by switches (SW) into a broader bus, which is only used when data must be transferred between different sets. Supply voltage of each sub-bus is adjustable and is set the lower the less traffic there is on the bus. The parallel transfer operation makes it possible to increase the transfer capacity of the bus structure without increasing it's clock frequency. Furthermore energy consumption can be reduced by dropping the supply voltage of the bus circuits so that the bus retains the transfer capacity needed.
摘要翻译：一种用于将总线适配到包括多个功能单元（311,312，，31n）和总线结构的系统中的数据业务的方法。功能单元被划分为至少两组，使得主要将数据彼此传输的单元属于同一组并且与相同的单独子总线（321; 322）接口。子总线可以通过开关（SW）组合成更宽的总线，仅在不同组之间传输数据时才使用。每个子总线的电源电压是可调的，并且设置在总线上的流量越少。并行传送操作使得可以增加总线结构的传输容量而不增加其时钟频率。此外，可以通过降低总线电路的电源电压来降低能量消耗，使得总线保持所需的传输容量。

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