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1. 发明申请

WO2011095678A1 UPDATE HANDLER FOR MULTI-CHANNEL CACHE 审中-公开
标题翻译：用于多通道高速缓存的更新操作
公开(公告)号：WO2011095678A1
公开(公告)日：2011-08-11
申请号：PCT/FI2011/050053
申请日：2011-01-25
申请人： NOKIA CORPORATION , AHO, Eero , NIKARA, Jari , KUUSILINNA, Kimmo
发明人： AHO, Eero , NIKARA, Jari , KUUSILINNA, Kimmo
IPC分类号： G06F12/08 , G06F12/10 , G06F11/10
CPC分类号： G06F12/0844 , G06F12/084 , G06F12/0846 , G06F12/0851 , G06F12/0859 , G06F12/0862 , G06F2212/1016 , G06F2212/601 , G06F2212/6042
摘要： Disclosed herein is a miss handler for a multi-channel cache memory, and a method that includes determining a need to update a multi-channel cache memory due at least to one of an occurrence of a cache miss or a data prefetch being needed. The method further includes operating a multi-channel cache miss handler to update at least one cache channel storage of the multi-channel cache memory from a main memory.
摘要翻译：本文公开了一种用于多通道高速缓冲存储器的未命中处理器，以及一种方法，其包括至少由于存在高速缓存未命中的发生或需要的数据预取而导致更新多通道高速缓冲存储器的需要。该方法还包括操作多通道高速缓存未命中处理程序以从主存储器更新多通道高速缓冲存储器的至少一个高速缓存通道存储器。

2. 发明申请

WO2011095677A1 CHANNEL CONTROLLER FOR MULTI-CHANNEL CACHE 审中-公开
标题翻译：多通道高速缓存的通道控制器
公开(公告)号：WO2011095677A1
公开(公告)日：2011-08-11
申请号：PCT/FI2011/050052
申请日：2011-01-25
申请人： NOKIA CORPORATION , NIKARA, Jari , AHO, Eero , KUUSILINNA, Kimmo
发明人： NIKARA, Jari , AHO, Eero , KUUSILINNA, Kimmo
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0864 , G06F12/084 , G06F12/0851 , G06F12/0893 , G06F12/1036 , G06F2212/1028 , G06F2212/1048 , G06F2212/301 , G06F2212/601 , G06F2212/6042 , Y02D10/13
摘要： Disclosed herein is a channel controller for a multi-channel cache memory, and a method that includes receiving a memory address associated with a memory access request to a main memory of a data processing system; translating the memory address to form a first access portion identifying at least one partition of a multi-channel cache memory, and at least one further access portion, where the at least one partition includes at least one channel; and applying the at least one further access portion to the at least one channel of the multi-channel cache memory.
摘要翻译：本文公开了一种用于多通道高速缓冲存储器的通道控制器，以及一种方法，其包括将与存储器访问请求相关联的存储器地址接收到数据处理系统的主存储器; 翻译存储器地址以形成识别多通道高速缓冲存储器的至少一个分区的第一访问部分和至少一个另外的访问部分，其中所述至少一个分区包括至少一个信道; 以及将所述至少一个另外的访问部分应用于所述多通道高速缓冲存储器的所述至少一个通道。

3. 发明申请

WO2011032593A1 MULTI-CHANNEL CACHE MEMORY 审中-公开
标题翻译：多通道高速缓存存储器
公开(公告)号：WO2011032593A1
公开(公告)日：2011-03-24
申请号：PCT/EP2009/062076
申请日：2009-09-17
申请人： NOKIA CORPORATION , NIKARA, Jari , AHO, Eero , KUUSILINNA, Kimmo
发明人： NIKARA, Jari , AHO, Eero , KUUSILINNA, Kimmo
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/084 , G06F12/0842 , G06F12/0844
摘要： A cache memory including:a plurality of parallel input ports configured to receive, in parallel, memory access requests wherein each parallel input port is operable to receive a memory access request for any one of a plurality of processing units; and a plurality of cache blocks wherein each cache block is configured to receive memory access requests from a unique one of the plurality of input ports such that there is a one-to-one mapping between the plurality of parallel input ports and the plurality of cache blocks and wherein each of the plurality of cache blocks is configured to serve a unique portion of an address space of the memory.
摘要翻译：一种高速缓冲存储器，包括：多个并行输入端口，被配置为并行地接收存储器访问请求，其中每个并行输入端口可操作以接收多个处理单元中的任何一个的存储器访问请求; 以及多个高速缓存块，其中每个高速缓存块被配置为从所述多个输入端口中的唯一的输入端口接收存储器访问请求，使得在所述多个并行输入端口和所述多个高速缓存器之间存在一对一映射块，并且其中所述多个高速缓存块中的每一个被配置为服务于所述存储器的地址空间的唯一部分。

4. 发明申请

WO2008119732A1 A MODULAR DEVICE COMPONENT 审中-公开
标题翻译：模块化器件组件
公开(公告)号：WO2008119732A1
公开(公告)日：2008-10-09
申请号：PCT/EP2008/053630
申请日：2008-03-27
申请人： NOKIA CORPORATION , KUUSILINNA, Kimmo , NIKARA, Jari , LIUHA, Petri
发明人： KUUSILINNA, Kimmo , NIKARA, Jari , LIUHA, Petri
IPC分类号： G06F15/17
CPC分类号： H04L69/12 , H04L47/125 , H04L47/726 , H04L49/90 , H04L49/9063 , H04L67/1002 , H04L67/1006 , H04L69/26
摘要： A component (23) of an electronic device comprises a network connection processor (27), which comprises a physical network connection block (31) to receive data from and transmit data to a network and a first data processor (27) configured to process data arriving at the network connection processor (27), and a second data processor (28) configured to process data received from the network connection processor (27).
摘要翻译：电子设备的组件（23）包括网络连接处理器（27），网络连接处理器（27）包括物理网络连接块（31），用于从网络接收数据并向网络发送数据;以及第一数据处理器（27），被配置为处理数据到达网络连接处理器（27），以及第二数据处理器（28），被配置为处理从网络连接处理器（27）接收的数据。

5. 发明申请

WO2008041069A3 3D CHIP ARRANGEMENT INCLUDING MEMORY MANAGER 审中-公开
公开(公告)号：WO2008041069A3
公开(公告)日：2008-04-10
申请号：PCT/IB2007/001818
申请日：2007-07-02
申请人： NOKIA CORPORATION , LAHTINEN, Vesa , HILL, Tapio , KUUSILINNA, Kimmo , NIKARA, Jari , KUULUSA, Mika , MÄKELÄINEN, Tommi
发明人： LAHTINEN, Vesa , HILL, Tapio , KUUSILINNA, Kimmo , NIKARA, Jari , KUULUSA, Mika , MÄKELÄINEN, Tommi
IPC分类号： G11C5/02 , H01L23/528
摘要： Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.

6. 发明申请

WO2009024201A2 METHODS AND SYSTEM FOR MODULAR DEVICE BOOTING 审中-公开
标题翻译：用于模块化设备引导的方法和系统
公开(公告)号：WO2009024201A2
公开(公告)日：2009-02-26
申请号：PCT/EP2008/004875
申请日：2008-06-17
申请人： NOKIA CORPORATION , KUUSILINNA, Kimmo , NIKARA, Jari , LAHTINEN, Vesa , LATVA-AHO, Antti
发明人： KUUSILINNA, Kimmo , NIKARA, Jari , LAHTINEN, Vesa , LATVA-AHO, Antti
IPC分类号： G06F9/445
CPC分类号： G06F9/4416 , G06F9/4401
摘要： The present invention a method for modular device booting comprising retrieving a first boot code from a non-volatile memory element, receiving a memory access request from at least one subsystem, said memory access including at least a boot status indication indicating a memory region and a memory address, if said received address and region match a predefined address and region, associating said at least one subsystem with a corresponding subsystem boot code address included in said retrieved first boot code, retrieving a corresponding subsystem boot code from said associated boot code address, and transferring said boot code to said corresponding subsystem.
摘要翻译：本发明提供了一种用于模块化设备引导的方法，包括从非易失性存储器元件中检索第一引导代码，从至少一个子系统接收存储器访问请求，所述存储器访问包括至少一个引导如果所述接收到的地址和区域匹配预定义的地址和区域，则将所述至少一个子系统与包括在所述检索到的第一引导代码中的对应的子系统引导代码地址相关联，检索对应的子系统引导来自所述相关联的引导代码地址的代码，并且将所述引导代码传送到所述相应的子系统。

7. 发明申请

WO2008041070A1 REALLOCATION OF MEMORY THROUGH GLOBAL ADDRESSING 审中-公开
标题翻译：通过全球化解决重读记忆
公开(公告)号：WO2008041070A1
公开(公告)日：2008-04-10
申请号：PCT/IB2007/001824
申请日：2007-07-03
申请人： NOKIA CORPORATION , LAHTINEN, Vesa , KUUSILINNA, Kimmo , NIKARA, Jari , NURMINEN, Jukka, M.
发明人： LAHTINEN, Vesa , KUUSILINNA, Kimmo , NIKARA, Jari , NURMINEN, Jukka, M.
IPC分类号： G06F12/06
CPC分类号： G06F12/0284 , G06F12/0653 , G06F2212/205 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Systems, apparatuses and methods for efficient logical memory management using centralized memory management. One embodiment involves allocating a first memory region to a first subsystem, generating a region code associated with the allocated memory region, storing the region code in connection with an address of the memory region, and defining the first subsystem as a first owner for the memory region by storing a unique subsystem identifier together with the region code in a parameter table. In this manner, a memory region may be globally addressed by its region code and an ownership to a subsystem is defined and stored.
摘要翻译：使用集中式内存管理的高效逻辑内存管理的系统，设备和方法。一个实施例涉及将第一存储器区域分配给第一子系统，生成与分配的存储器区域相关联的区域代码，存储与存储器区域的地址有关的区域代码，以及将第一子系统定义为存储器的第一所有者通过在参数表中存储唯一的子系统标识符和区域代码。以这种方式，可以通过其区域代码对存储器区域进行全局寻址，并且定义并存储对子系统的所有权。

8. 发明申请

WO2014033347A1 METHOD AND APPARATUS FOR RECORDING VIDEO SEQUENCES 审中-公开
标题翻译：记录视频序列的方法和装置
公开(公告)号：WO2014033347A1
公开(公告)日：2014-03-06
申请号：PCT/FI2012/050811
申请日：2012-08-27
申请人： NOKIA CORPORATION , NIKARA, Jari , PESONEN, Mika , AHO, Eero
发明人： NIKARA, Jari , PESONEN, Mika , AHO, Eero
IPC分类号： H04N5/225 , H04N5/232 , H04N1/21 , G06F3/041
CPC分类号： H04N5/91 , G06F3/04847 , G06F3/0488 , H04N5/23206 , H04N5/23216 , H04N5/23293 , H04N5/772
摘要： A method for recording a video sequence comprises: - receiving a first instruction, which defines the position of a first boundary with respect to a preview image, - receiving a second instruction, which defines the position of a second boundary, - determining the position of a first sensor portion according the position of the first boundary, - determining the position of a second sensor portion according the second instruction, - providing first sensor data by forming a first optical image on an image sensor, - providing second sensor data by forming a second optical image on the image sensor, - determining a first image frame from the first sensor data obtained from the first sensor portion, - determining a second image frame from the second sensor data obtained from the second sensor portion, and - storing the first image frame and the second image frame.
摘要翻译：一种用于记录视频序列的方法包括： - 接收定义相对于预览图像的第一边界的位置的第一指令， - 接收限定第二边界的位置的第二指令， - 确定第二边界的位置根据第一边界的位置的第一传感器部分， - 根据第二指令确定第二传感器部分的位置， - 通过在图像传感器上形成第一光学图像来提供第一传感器数据， - 通过形成第二传感器数据在所述图像传感器上的第二光学图像， - 根据从所述第一传感器部分获得的所述第一传感器数据确定第一图像帧， - 从所述第二传感器部分获得的所述第二传感器数据确定第二图像帧，以及 - 存储所述第一图像帧和第二图像帧。

9. 发明申请

WO2012098428A1 TASK PERFORMANCE 审中-公开
标题翻译：任务执行
公开(公告)号：WO2012098428A1
公开(公告)日：2012-07-26
申请号：PCT/IB2011/050219
申请日：2011-01-18
申请人： NOKIA CORPORATION , NIKARA, Jari , AHO, Eero , PESONEN, Mika , STANEK, Zbigniew
发明人： NIKARA, Jari , AHO, Eero , PESONEN, Mika , STANEK, Zbigniew
IPC分类号： G06F3/023 , G06F3/048
CPC分类号： G06F9/46 , G06F1/1643 , G06F3/017 , G06F3/048 , G06F2203/0381
摘要： A method including: identifying, for a current user input state, a plurality of available next user input states; defining a set of putative next user input states comprising one or more of the available next user input states; defining a set of advancing tasks comprising one or more advancing tasks, in anticipation of the current user input state becoming, next, any one of the one or more putative next user input states of the set of putative next user input states; redefining the set of putative next user input states, comprising one or more of the available next user input states, in response to a user movement signal that depends upon user movement; and redefining the set of advancing tasks comprising one or more advancing tasks, in anticipation of the current user input state becoming, next, any one of the one or more putative next user input states of the set of putative next user input states.
摘要翻译：一种方法，包括：针对当前用户输入状态识别多个可用的下一个用户输入状态; 定义包括所述可用下一个用户输入状态中的一个或多个的一组推定的下一个用户输入状态; 定义包括一个或多个前进任务的一组前进任务，预期当前用户输入状态成为下一个用户输入状态集合中的一个或多个推定的下一个用户输入状态中的任何一个; 响应于取决于用户移动的用户移动信号，重新定义一组推定的下一个用户输入状态，包括一个或多个可用的下一个用户输入状态; 并且重新定义包括一个或多个前进任务的一组前进任务，以预期当前用户输入状态成为下一个用户输入状态集中的一个或多个推定的下一个用户输入状态中的任何一个。

10. 发明申请

WO2011104678A1 SYSTEMS, METHODS, AND APPARATUSES FOR FACILITATING TARGETED COMPILATION OF SOURCE CODE 审中-公开
标题翻译：促进目标编码源代码的系统，方法和装置
公开(公告)号：WO2011104678A1
公开(公告)日：2011-09-01
申请号：PCT/IB2011/050764
申请日：2011-02-24
申请人： NOKIA CORPORATION , NIKARA, Jari , AHO, Eero , LEPPANEN, Tapani
发明人： NIKARA, Jari , AHO, Eero , LEPPANEN, Tapani
IPC分类号： G06F9/45
CPC分类号： G06F8/47
摘要： Methods, apparatuses, and systems are provided for facilitating targeted compilation of source code. A method may include receiving source code for an application. The method may further include determining information about an execution platform of an end user apparatus on which the application will be executed. The method may additionally include compiling the source code based at least in part on the determined information into an executable targeted to the execution platform of the end user apparatus. The method may also include causing the executable to be sent to the end user apparatus. Corresponding apparatuses and systems are also provided.
摘要翻译：提供了方法，设备和系统，以便于有针对性地编译源代码。方法可以包括接收应用的源代码。该方法还可以包括确定关于将在其上执行应用的最终用户装置的执行平台的信息。该方法可以另外包括至少部分地基于所确定的信息将源代码编译成针对终端用户装置的执行平台的可执行文件。该方法还可以包括使得可执行文件被发送到最终用户装置。还提供了相应的装置和系统。

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