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1. 发明申请

WO2011071966A3 CROSS-POINT DIODE ARRAYS AND METHODS OF MANUFACTURING CROSS-POINT DIODE ARRAYS 审中-公开
标题翻译：交叉点二极管阵列和制造交叉点二极管阵列的方法
公开(公告)号：WO2011071966A3
公开(公告)日：2011-11-17
申请号：PCT/US2010059362
申请日：2010-12-08
申请人： MICRON TECHNOLOGY INC , ZAHURAK JOHN , TANG SANH D , SANDHU GURTEJ S
发明人： ZAHURAK JOHN , TANG SANH D , SANDHU GURTEJ S
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L21/823487 , H01L21/823412 , H01L21/823418 , H01L27/105 , H01L27/24 , H01L29/66666 , H01L29/7827
摘要： Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.
摘要翻译：形成具有支柱的存储单元阵列和存储单元的方法。各个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。源区可以在柱的列之间，并且栅极线沿着柱的一列延伸并且与相应的源区隔开。每条栅极线沿着一列支柱围绕一部分半导体柱。可以选择性地去除牺牲帽结构，从而形成暴露相应半导体柱的顶部的自对准开口。形成在自对准开口中的各个漏极触点电连接到对应的半导体柱。

2. 发明申请

WO2012006094A3 THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD 审中-公开
标题翻译：晶闸管随机存取存储器件和方法
公开(公告)号：WO2012006094A3
公开(公告)日：2012-04-26
申请号：PCT/US2011042196
申请日：2011-06-28
申请人： MICRON TECHNOLOGY INC , TANG SANH D , ZAHURAK JOHN K , VIOLETTE MICHAEL P
发明人： TANG SANH D , ZAHURAK JOHN K , VIOLETTE MICHAEL P
IPC分类号： H01L27/105 , H01L21/332 , H01L21/8239 , H01L27/108
CPC分类号： H01L29/66363 , H01L27/1027 , H01L29/42308 , H01L29/74 , H01L2924/1301
摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
摘要翻译：显示了存储器件和制造存储器件的方法。所示的方法和配置提供折叠和垂直存储器装置以提高存储密度。所提供的方法减少了对诸如深掺杂剂植入物之类的制造方法的需求。

3. 发明申请

WO2012009140A3 THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：三维存储器及其形成方法
公开(公告)号：WO2012009140A3
公开(公告)日：2012-06-21
申请号：PCT/US2011041888
申请日：2011-06-24
申请人： MICRON TECHNOLOGY INC , TANG SANH D , ZAHURAK JOHN K
发明人： TANG SANH D , ZAHURAK JOHN K
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11582 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2213/71 , H01L21/28273 , H01L21/76838 , H01L23/528 , H01L27/0688 , H01L27/11519 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/2454 , H01L27/249 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/06
摘要： Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.
摘要翻译：一些实施例包括存储设备和形成存储设备的方法。一个这样的存储器件包括第一组存储器单元，第一组的每个存储器单元形成在位于存储器件的一个器件层中的第一控制栅的空腔中。存储器件还包括第二组存储器单元，第二组的每个存储器单元形成在位于存储器件的另一个器件层中的第二控制栅的腔中。描述了附加的装置和方法。

4. 发明申请

WO2012116207A3 CHARGE STORAGE APPARATUS, SYSTEMS AND METHODS 审中-公开
标题翻译：电荷存储装置，系统和方法
公开(公告)号：WO2012116207A3
公开(公告)日：2012-12-06
申请号：PCT/US2012026358
申请日：2012-02-23
申请人： MICRON TECHNOLOGY INC , TANG SANH D , ZAHURAK JOHN K
发明人： TANG SANH D , ZAHURAK JOHN K
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11524 , H01L27/11578 , H01L27/11582 , H01L29/04 , H01L29/167 , H01L29/495 , H01L29/4966 , H01L29/7889 , H01L29/792 , H01L29/7926
摘要： Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.
摘要翻译：描述形成多层半导体器件的方法以及包括它们的设备和系统。在一种这样的方法中，在一层半导体材料和一层电介质中形成开口。处理由开口暴露的半导体材料层的一部分，使得该部分被掺杂成与层中剩余的半导体材料不同。该层的至少基本上全部剩余的半导体材料被移除，留下该层半导体材料的不同掺杂部分作为电荷存储结构。隧穿电介质形成在电荷存储结构的第一表面上，并且栅间电介质形成在电荷存储结构的第二表面上。还描述了另外的实施例。

5. 发明申请

WO2011109149A3 FLOATING BODY CELL STRUCTURES, DEVICES INCLUDING SAME, AND METHODS FOR FORMING SAME 审中-公开
标题翻译：浮动体细胞结构，包括其的装置及其形成方法
公开(公告)号：WO2011109149A3
公开(公告)日：2011-11-17
申请号：PCT/US2011024387
申请日：2011-02-10
申请人： MICRON TECHNOLOGY INC , TANG SANH D , ZAHURAK JOHN K , JUENGLING WERNER
发明人： TANG SANH D , ZAHURAK JOHN K , JUENGLING WERNER
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10802 , H01L21/845 , H01L27/10826 , H01L27/10879 , H01L27/1211 , H01L29/4236 , H01L29/7841
摘要： Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.
摘要翻译：包括浮置体细胞结构，其包括布置在背栅上的浮体阵列阵列和与后门间隔开的浮体细胞的源区和漏区。浮体细胞可以各自包括体积的半导体材料，其具有在柱之间延伸的通道区域，其可以通过诸如U形沟槽的空隙分开。阵列的浮体电池可以电耦合到另一个栅极，另一个栅极可以设置在半导体材料的体积的侧壁上或其内的空隙中。还公开了形成浮体电池器件的方法。

6. 发明申请

WO2011053731A3 METHODS, STRUCTURES AND DEVICES FOR INCREASING MEMORY DENSITY 审中-公开
标题翻译：用于增加记忆密度的方法，结构和设备
公开(公告)号：WO2011053731A3
公开(公告)日：2011-09-29
申请号：PCT/US2010054564
申请日：2010-10-28
申请人： MICRON TECHNOLOGY INC , TANG SANH D , ZAHURAK JOHN K
发明人： TANG SANH D , ZAHURAK JOHN K
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/2409 , H01L21/22 , H01L27/0207 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： Non volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non volatile memory devices as well as intermediate structures are also disclosed.
摘要翻译：包括包括多个垂直叠加的二极管的存储器串的非易失性存储器件。每个二极管可以沿着电极的长度布置在不同的位置处，并且可以通过介电材料与相邻的二极管间隔开。电极可以将存储器串的二极管彼此电耦合到另一个存储器件，例如MOSFET器件。还公开了形成非易失性存储器件以及中间结构的方法。

7. 发明申请

WO2011109146A2 SEMICONDUCTOR-METAL-ON-INSULATOR STRUCTURES, METHODS OF FORMING SUCH STRUCTURES, AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES 审中-公开
标题翻译：半导体金属绝缘体结构，形成这种结构的方法和包括这种结构的半导体器件
公开(公告)号：WO2011109146A2
公开(公告)日：2011-09-09
申请号：PCT/US2011024354
申请日：2011-02-10
申请人： MICRON TECHNOLOGY INC , TANG SANH D , ZHANG MING , BAYLESS ANDREW M , ZAHURAK JOHN K
发明人： TANG SANH D , ZHANG MING , BAYLESS ANDREW M , ZAHURAK JOHN K
CPC分类号： H01L27/1203 , H01L21/02532 , H01L21/02592 , H01L21/30604 , H01L21/76251 , H01L21/76254 , H01L21/84 , H01L27/1021 , H01L27/10802 , H01L27/12 , H01L27/24 , H01L29/04 , H01L29/16 , H01L29/7841 , H01L29/78603 , H01L29/78642 , H01L29/78645 , H01L29/78648
摘要： Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures.
摘要翻译：制造半导体绝缘体上金属（SMOI）结构的方法包括在第一半导体衬底上形成包括绝缘体材料的受主晶片，在第二半导体衬底上形成包括导电材料和非晶硅材料的施主晶片，以及键合施主晶片的非晶硅材料到受主晶片的绝缘体材料。还公开了由这些方法形成的SMOI结构，以及包括这种SMOI结构的半导体器件。

8. 发明申请

WO2012125610A3 METHODS OF FORMING AT LEAST ONE CONDUCTIVE ELEMENT, METHODS OF FORMING A SEMICONDUCTOR STRUCTURE, METHODS OF FORMING A MEMORY CELL AND RELATED SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：形成至少一个导电元件的方法，形成半导体结构的方法，形成存储单元的方法和相关的半导体结构
公开(公告)号：WO2012125610A3
公开(公告)日：2012-12-06
申请号：PCT/US2012028878
申请日：2012-03-13
申请人： MICRON TECHNOLOGY INC , TANG SANH D , SILLS SCOTT E , WEST WHITNEY L , GOODWIN ROB B , SINHA NISHANT
发明人： TANG SANH D , SILLS SCOTT E , WEST WHITNEY L , GOODWIN ROB B , SINHA NISHANT
IPC分类号： H01L21/28 , H01L21/8239
CPC分类号： H01L45/1266 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76858 , H01L21/76877 , H01L21/76882 , H01L21/76883 , H01L23/53247 , H01L23/53252 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.
摘要翻译：形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。可以进行退火处理以形成银和材料的混合物或合金。该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。所得的导电元件具有所需的电阻率。所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。还公开了一种半导体结构和包括这种导电结构的存储单元。

9. 发明申请

WO2012030379A3 PHASE CHANGE MEMORY STRUCTURES AND METHODS 审中-公开
标题翻译：相变记忆结构与方法
公开(公告)号：WO2012030379A3
公开(公告)日：2012-05-24
申请号：PCT/US2011001483
申请日：2011-08-24
申请人： MICRON TECHNOLOGY INC , TANG SANH D
发明人： TANG SANH D
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L45/1253 , G11C13/0004 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1683
摘要： Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.
摘要翻译：本文描述了与相变材料存储器相关联的方法，装置和系统。在一个或多个实施例中，形成相变材料存储单元的方法包括形成多个存储器结构区域，其中存储器结构区域包括底部电极材料和牺牲材料，在多个绝缘体区域之间形成多个绝缘体区域存储器结构区域，在多个绝缘体区域之间形成多个开口，并通过去除牺牲材料和绝缘体区域的数量的一部分在绝缘体区域的数量上形成轮廓表面，在数量上形成多个电介质间隔物的绝缘体区域之间，在多个绝缘体区域之间形成轮廓的开口，并通过去除一部分电介质间隔物而露出底部电极材料，并且在绝缘体区域之间的开口中形成相变材料。

10. 发明申请

WO2012003224A3 MEMORIES AND THEIR FORMATION 审中-公开
标题翻译：记忆及其形成
公开(公告)号：WO2012003224A3
公开(公告)日：2012-03-01
申请号：PCT/US2011042392
申请日：2011-06-29
申请人： MICRON TECHNOLOGY INC , TANG SANH D , SINHA NISHANT
发明人： TANG SANH D , SINHA NISHANT
IPC分类号： G11C7/18 , G11C16/02 , H01L27/115
CPC分类号： H01L27/11551 , G11C16/0483 , H01L27/11578
摘要： Memories and their formation are disclosed. One such memory has first and second memory cells at a first vertical level of the memory, first and second memory cells at a second vertical level of the memory, a first data line is selectively coupled to the first memory cells at the first and second vertical levels, and a second data line over the first data line is selectively coupled to the second memory cells at the first and second vertical levels.
摘要翻译：记忆及其形成被披露。一个这样的存储器具有位于存储器的第一垂直级的第一和第二存储器单元，位于存储器的第二垂直级的第一和第二存储单元，第一数据线在第一和第二垂直方向选择性地耦合到第一存储器单元电平和第一数据线上的第二数据线在第一和第二垂直电平选择性地耦合到第二存储器单元。

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