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1. 发明申请

WO2010141059A3 METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND SYSTEMS 审中-公开
标题翻译：用于利用存储器件和系统来控制存储器存取的方法
公开(公告)号：WO2010141059A3
公开(公告)日：2011-03-03
申请号：PCT/US2010001521
申请日：2010-05-24
申请人： MICRON TECHNOLOGY INC , GALBO NEAL A , FEELEY PETER , RADKE WILLIAM H , TSAI VICTOR Y , LEIBOWITZ ROBERT N
发明人： GALBO NEAL A , FEELEY PETER , RADKE WILLIAM H , TSAI VICTOR Y , LEIBOWITZ ROBERT N
IPC分类号： G06F13/16 , G06F12/00 , G06F13/38
CPC分类号： G06F3/0604 , G06F3/0659 , G06F3/0683 , G06F13/1642
摘要： The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.
摘要翻译：本公开包括用于使用存储设备，系统，主机控制器和存储设备来控制主机存储器访问的方法。用于使用存储器设备控制主机存储器访问的一个实施例包括从主机接收至少一个命令并且利用存储器设备控制至少一个命令的执行。

2. 发明申请

WO2010085340A3 HOST CONTROLLER 审中-公开
标题翻译：主控制器
公开(公告)号：WO2010085340A3
公开(公告)日：2010-10-21
申请号：PCT/US2010000150
申请日：2010-01-21
申请人： MICRON TECHNOLOGY INC , FEELEY PETER , LEIBOWITZ ROBERT N , RADKE WILLIAM H , GALBO NEAL A , TSAI VICTOR Y
发明人： FEELEY PETER , LEIBOWITZ ROBERT N , RADKE WILLIAM H , GALBO NEAL A , TSAI VICTOR Y
IPC分类号： G06F13/10 , G06F12/00
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0685 , G06F13/28 , G06F13/32 , G06F13/385 , G06F13/4282
摘要： The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.
摘要翻译：本公开包括用于控制存储器设备的方法，设备和系统。一种用于控制存储器设备实施例的方法包括：将设备类相关信息和命令存储在主机系统存储器和主机控制器存储器中的一个或多个中;将指向该命令的指针设置在主机控制器中的寄存器中;指向对一个存储器的访问; 通过主机控制器将更多的主机系统存储器和主机控制器存储器与存储器设备相连; 并用存储设备执行该命令。

3. 发明申请

WO2011019372A2 PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL 审中-公开
标题翻译：分组解密/重建和链路控制
公开(公告)号：WO2011019372A2
公开(公告)日：2011-02-17
申请号：PCT/US2010002186
申请日：2010-08-06
申请人： MICRON TECHNOLOGY INC , RADKE WILLIAM H , TSAI VICTOR Y , FEELEY PETER , GALBO NEAL A , LEIBOWITZ ROBERT N
发明人： RADKE WILLIAM H , TSAI VICTOR Y , FEELEY PETER , GALBO NEAL A , LEIBOWITZ ROBERT N
IPC分类号： H04L12/56 , H04L29/06
CPC分类号： H04L47/34 , H04L1/1867 , H04L47/27 , H04L69/324
摘要： The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.
摘要翻译：本公开包括用于分组处理的方法，设备和系统。用于分组流控制的一个方法实施例包括将传输层分组解构成多个链路控制层分组，其中每个链路控制层分组具有相关联的序列号，经由公共链路传送该链路控制层分组的数量用于多个外围设备的物理连接，以及在通信期间限制未完成的链路控制层分组的数量。

4. 发明申请

WO2010141058A2 OBJECT ORIENTED MEMORY IN SOLID STATE DEVICES 审中-公开
标题翻译：在固态设备中的面向对象的存储器
公开(公告)号：WO2010141058A2
公开(公告)日：2010-12-09
申请号：PCT/US2010001520
申请日：2010-05-24
申请人： MICRON TECHNOLOGY INC , FEELEY PETER , GALBO NEAL A , COOKE JAMES , TSAI VICTOR Y , LEIBOWITZ ROBERT N , RADKE WILLIAM H
发明人： FEELEY PETER , GALBO NEAL A , COOKE JAMES , TSAI VICTOR Y , LEIBOWITZ ROBERT N , RADKE WILLIAM H
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F11/1068 , G06F11/2064 , G06F12/0246 , G11C29/52
摘要： The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks.
摘要翻译：本公开包括固态设备中用于面向对象的存储器的方法，设备和系统。在固态设备中面向对象存储器的方法的一个实施例包括以原子操作方式访问定义的数据集作为单个对象，其中访问来自除主机之外的源。该实施例还包括将定义的一组数据作为单个对象存储在通过包括固态存储器块的数量的固态设备的控制部件格式化的多个固态存储器块中。

5. 发明申请

WO2011129874A2 BOOT PARTITIONS IN MEMORY DEVICES AND SYSTEMS 审中-公开
标题翻译：内存设备和系统中的引导分区
公开(公告)号：WO2011129874A2
公开(公告)日：2011-10-20
申请号：PCT/US2011000651
申请日：2011-04-11
申请人： MICRON TECHNOLOGY INC , GALBO NEAL A , TSAI VICTOR Y , RADKE WILLIAM H , DATLA KRISHNAM R
发明人： GALBO NEAL A , TSAI VICTOR Y , RADKE WILLIAM H , DATLA KRISHNAM R
IPC分类号： G06F12/02
CPC分类号： G06F9/5077 , G06F3/062 , G06F3/0644 , G06F3/0679 , G06F9/4401 , G06F12/0246 , G06F2212/7206
摘要： The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.
摘要翻译：本公开包括存储器设备和系统中的引导分区以及与其相关联的方法。一个或多个实施例包括存储器单元的阵列，其中阵列包括引导分区和多个附加分区。顺序逻辑单元标识符与附加分区相关联，并且与顺序逻辑单元标识符不一致的逻辑单元标识符与引导分区相关联。

6. 发明申请

WO2010141208A2 ADVANCED DETECTION OF MEMORY DEVICE REMOVAL, AND METHODS, DEVICES AND CONNECTORS 审中-公开
标题翻译：高级检测存储器件移除，以及方法，器件和连接器
公开(公告)号：WO2010141208A2
公开(公告)日：2010-12-09
申请号：PCT/US2010035241
申请日：2010-05-18
申请人： MICRON TECHNOLOGY INC , COOKE JAMES , FEELEY PETER , TSAI VICTOR , RADKE WILLIAM H , GALBO NEAL , COBBLEY CHAD
发明人： COOKE JAMES , FEELEY PETER , TSAI VICTOR , RADKE WILLIAM H , GALBO NEAL , COBBLEY CHAD
IPC分类号： G06F13/14 , G06F1/32
CPC分类号： G06F13/4068
摘要： Memory devices, connectors, methods for terminating an operation are provided, including memory device configured to terminate internal operation such as programming or erase operation responsive to receiving a signal during removal of the memory device from a connector, such as a socket. The memory device may be specially configured to generate the removal signal, such as by including a dedicated removal terminal. The memory card may respond to the signal by terminating a programming or erase operation before power is lost. Removal terminal may have a dimension different from a dimension of a power terminal through which the memory device receives power. The connector may be specially configured to generate a signal that causes a host to terminate programming or erase operations in the memory device prior to memory card removal, such as by including a switch that is actuated when the memory device moves to pre-power loss position.
摘要翻译：提供了用于终止操作的存储器件，连接器，用于终止操作的方法，包括响应于在从诸如插座的连接器移除存储器件期间接收到信号而终止诸如编程或擦除操作的内部操作的存储器件。存储器件可以被特别地配置为产生去除信号，例如通过包括专用的移除终端。存储卡可以通过在断电之前终止编程或擦除操作来响应信号。移除终端可以具有与存储设备通过其接收电力的电源终端的维度不同的维度。连接器可以被特别地配置成产生一个信号，使得主机在存储卡移除之前终止在存储器装置中的编程或擦除操作，例如通过包括在存储器件移动到功率损耗位置时启动的开关。

7. 发明申请

WO2012097136A2 METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES 审中-公开
标题翻译：用于调节器件中的感测电压的方法，器件和系统
公开(公告)号：WO2012097136A2
公开(公告)日：2012-07-19
申请号：PCT/US2012021054
申请日：2012-01-12
申请人： MICRON TECHNOLOGY INC , RADKE WILLIAM H , SHEN ZHENLEI , FEELEY PETER
发明人： RADKE WILLIAM H , SHEN ZHENLEI , FEELEY PETER
IPC分类号： G11C16/34 , G11C16/26
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/0483 , G11C16/26
摘要： The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.
摘要翻译：本公开包括用于调整装置中的感测电压的方法，装置和系统。一个或多个实施例包括存储器单元和被配置为使用感测电压对存储器单元执行感测操作以确定具有大于感测电压的阈值电压（Vt）的存储器单元的数量并且调整感测电压用于至少部分地基于所确定的存储器单元的数量来确定存储器单元的状态。

8. 发明申请

WO2011142799A3 DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS 审中-公开
标题翻译：在存储器件和系统中确定和使用软数据
公开(公告)号：WO2011142799A3
公开(公告)日：2012-01-05
申请号：PCT/US2011000761
申请日：2011-05-02
申请人： MICRON TECHNOLOGY INC , RADKE WILLIAM H , SHEN ZHENLEI , FEELEY PETER
发明人： RADKE WILLIAM H , SHEN ZHENLEI , FEELEY PETER
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/26 , G11C7/14 , G11C11/26 , G11C11/5628 , G11C11/5642 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004
摘要： The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.
摘要翻译：本公开包括用于在存储器设备和系统中确定和使用软数据的方法，设备和系统。一个或多个实施例包括耦合到阵列的存储器单元阵列和控制电路。控制电路被配置为使用多个感测电压对存储器单元执行多个感测操作，以确定与存储器单元的目标状态相关联的软数据，并且基于以下方式调整用于确定目标状态的感测电压：最少部分地在确定的软数据上。

9. 发明申请

WO2013006354A3 PROGRAMMING METHODS AND MEMORIES 审中-公开
标题翻译：程序设计方法和记忆
公开(公告)号：WO2013006354A3
公开(公告)日：2013-03-28
申请号：PCT/US2012044519
申请日：2012-06-28
申请人： MICRON TECHNOLOGY INC , SARIN VISHAL , RADKE WILLIAM H , ROOHPARVAR FRANKIE F
发明人： SARIN VISHAL , RADKE WILLIAM H , ROOHPARVAR FRANKIE F
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454
摘要： Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
摘要翻译：公开了编程存储器和存储器的方法。在至少一个实施例中，通过确定选定单元的预目标阈值电压来编程存储器，其中使用预选目标单元的至少一个邻近单元的预目标阈值电压值来确定预目标阈值电压。

10. 发明申请

WO2009155022A3 HYBRID MEMORY MANAGEMENT 审中-公开
标题翻译：混合记忆管理
公开(公告)号：WO2009155022A3
公开(公告)日：2010-03-04
申请号：PCT/US2009045386
申请日：2009-05-28
申请人： MICRON TECHNOLOGY INC , RADKE WILLIAM H , MURRAY MICHAEL , FURUHJELM MARTIN RAGNAR , GELDMAN JOHN
发明人： RADKE WILLIAM H , MURRAY MICHAEL , FURUHJELM MARTIN RAGNAR , GELDMAN JOHN
IPC分类号： G06F12/00 , G06F12/06 , G11C16/00
CPC分类号： G06F12/0246 , G06F2212/1016 , G06F2212/1036 , G06F2212/7201 , G06F2212/7211 , G11C16/349 , G11C2211/5641
摘要： Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.
摘要翻译：用于使用单级和多级存储器单元的混合存储器件中的数据存储管理方法和装置。逻辑地址可以基于执行的写操作的频率在单级和多级存储器单元之间分配。可以通过各种方法来确定与存储器中的逻辑地址相对应的数据的初始存储，包括首先将所有数据写入单级存储器或者首先将所有数据写入多级存储器。其他方法允许主机根据预期用途将逻辑地址写入指向单级或多级存储器单元。

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