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1. 发明申请

WO2013006354A3 PROGRAMMING METHODS AND MEMORIES 审中-公开
标题翻译：程序设计方法和记忆
公开(公告)号：WO2013006354A3
公开(公告)日：2013-03-28
申请号：PCT/US2012044519
申请日：2012-06-28
申请人： MICRON TECHNOLOGY INC , SARIN VISHAL , RADKE WILLIAM H , ROOHPARVAR FRANKIE F
发明人： SARIN VISHAL , RADKE WILLIAM H , ROOHPARVAR FRANKIE F
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454
摘要： Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
摘要翻译：公开了编程存储器和存储器的方法。在至少一个实施例中，通过确定选定单元的预目标阈值电压来编程存储器，其中使用预选目标单元的至少一个邻近单元的预目标阈值电压值来确定预目标阈值电压。

2. 发明申请

WO2009073162A3 SENSING MEMORY CELLS 审中-公开
标题翻译：感应记忆细胞
公开(公告)号：WO2009073162A3
公开(公告)日：2009-08-27
申请号：PCT/US2008013255
申请日：2008-12-01
申请人： MICRON TECHNOLOGY INC , SARIN VISHAL , HOEI JUNG SHENG , ROOHPARVAR FRANKIE F , MAROTTA GIULIO-GIUSEPPE
发明人： SARIN VISHAL , HOEI JUNG SHENG , ROOHPARVAR FRANKIE F , MAROTTA GIULIO-GIUSEPPE
IPC分类号： G11C16/26 , G11C16/02 , G11C16/30
CPC分类号： G11C16/12 , G11C7/16 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5621 , G11C2211/5634 , G11C2211/5642
摘要： The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage (503) to a control gate of a memory cell (505) and to an analog- to-digital converter (ADC) (507). The aforementioned embodiment of a method also includes detecting an output of the ADC (515) at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry (511).
摘要翻译：本公开包括用于操作存储器单元的方法，器件，模块和系统。一个方法实施例包括将斜坡电压（503）施加到存储器单元（505）的控制栅极和模数转换器（ADC）（507）。方法的上述实施例还包括至少部分地响应于斜坡电压何时使存储器单元使感测电路（511）跳闸而检测ADC（515）的输出。

3. 发明申请

WO2009035504A8 REDUCING NOISE IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：减少半导体器件中的噪声
公开(公告)号：WO2009035504A8
公开(公告)日：2009-05-14
申请号：PCT/US2008010047
申请日：2008-08-25
申请人： MICRON TECHNOLOGY INC , SARIN VISHAL , ROOHPARVAR FRANKIE F , HOEI JUNG SHENG
发明人： SARIN VISHAL , ROOHPARVAR FRANKIE F , HOEI JUNG SHENG
IPC分类号： G11C16/00 , G11C16/06
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3418
摘要： The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
摘要翻译：本公开包括用于降低半导体器件中的噪声的方法，装置，模块和系统。一个方法实施例包括将复位电压施加到半导体器件的控制栅极一段时间。该方法还包括在施加复位电压之后感测半导体器件的状态。

4. 发明申请

WO2008157037A2 COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY 审中-公开
标题翻译：在固态存储器中的粗略和精细编程
公开(公告)号：WO2008157037A2
公开(公告)日：2008-12-24
申请号：PCT/US2008065751
申请日：2008-06-04
申请人： MICRON TECHNOLOGY INC , ROOHPARVAR FRANKIE F , SARIN VISHAL , HOEI JUNG-SHENG
发明人： ROOHPARVAR FRANKIE F , SARIN VISHAL , HOEI JUNG-SHENG
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3418
摘要： Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.
摘要翻译：适于接收和发送表示两个或多个位的位模式的模拟数据信号的存储器件有助于相对于传送指示各个位的数据信号的器件的数据传输速率的增加。这种存储器件的编程包括：用粗略的编程脉冲对单元进行初始编程，使其阈值电压以接近编程状态的大步进移动。然后使用粗略编程对相邻单元进行编程。然后，该算法返回到初始编程的单元，然后使用一个或多个精细脉冲编程，该精细脉冲以较小步长将阈值电压缓慢移动到最终编程状态阈值电压。

5. 发明申请

WO2009126516A3 ANALOG READ AND WRITE PATHS IN A SOLID STATE MEMORY DEVICE 审中-公开
标题翻译：模拟读取和写入状态在固态存储器件中
公开(公告)号：WO2009126516A3
公开(公告)日：2010-01-07
申请号：PCT/US2009039387
申请日：2009-04-03
申请人： MICRON TECHNOLOGY INC , ROOHPARVAR FRANKIE F , SARIN VISHAL
发明人： ROOHPARVAR FRANKIE F , SARIN VISHAL
IPC分类号： G06F13/16 , G06F12/00 , G06F13/38
CPC分类号： G11C7/10 , G11C7/1048 , G11C11/5628 , G11C16/0483 , G11C27/005 , G11C27/02 , G11C2207/101 , G11C2211/5621
摘要： A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface is comprised of a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.
摘要翻译：存储器件中的存储器阵列被耦合到模拟I / O数据接口，使得能够将模拟电压电平写入存储器阵列。 I / O接口包括多个模拟数据路径，每个模拟数据路径包括用于存储对应于目标电压的电荷的电容器，耦合到其相应数据路径的所选择的存储器单元将被编程到该目标电压。多个比较器可以包括在I / O接口中，每个这样的比较器耦合到相应的位线。这样的比较器可以将所选存储单元的阈值电压与其目标电压进行比较，并且当阈值电压等于或超过目标电压时禁止进一步的编程。

6. 发明申请

WO2007133645A3 NAND ARCHITECTURE MEMORY DEVICES AND OPERATION 审中-公开
标题翻译： NAND架构存储器件和操作
公开(公告)号：WO2007133645A3
公开(公告)日：2008-04-17
申请号：PCT/US2007011324
申请日：2007-05-10
申请人： MICRON TECHNOLOGY INC , ROOHPARVAR FRANKIE F
发明人： ROOHPARVAR FRANKIE F
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device.
摘要翻译：利用修改的NAND架构的非易失性存储器件，其存储器单元的NAND串的端部选择性地耦合到不同的位线可以有助于与传统的NAND存储器阵列架构相比增加的存储器密度，减少的制造步骤和更快的读取操作。可以以与传统NAND存储器阵列相同的方式来实现存储器单元的编程和擦除。然而，可以使用类似于DRAM设备中的读取操作的电荷共享技术来实现对存储器单元的读取。

7. 发明申请

WO2007103045A3 NAND MEMORY DEVICE COLUMN CHARGING 审中-公开
标题翻译： NAND存储器器件列充电
公开(公告)号：WO2007103045A3
公开(公告)日：2007-10-25
申请号：PCT/US2007004990
申请日：2007-02-27
申请人： MICRON TECHNOLOGY INC , ROOHPARVAR FRANKIE F
发明人： ROOHPARVAR FRANKIE F
IPC分类号： G11C16/04 , G11C7/12 , G11C11/56
CPC分类号： G11C7/02 , G11C7/1048 , G11C7/12 , G11C16/0483 , G11C16/24
摘要： Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations.
摘要翻译： NAND闪存设备和方法的实施例认识到，通过维持阵列的相邻列上的源电压可以减少有效的列耦合电容。在阵列操作（读取，写入和编程）之前将列保持在充电状态可以减少电流浪涌并改善数据读取时序。设备和方法通过预充电和阵列访问操作为阵列列充电。

8. 发明申请

WO2008151262A3 SOLID STATE MEMORY UTILIZING ANALOG COMMUNICATION OF DATA VALUES 审中-公开
标题翻译：使用数据值模拟通信的固态存储器
公开(公告)号：WO2008151262A3
公开(公告)日：2009-02-26
申请号：PCT/US2008065846
申请日：2008-06-05
申请人： MICRON TECHNOLOGY INC , ROOHPARVAR FRANKIE F
发明人： ROOHPARVAR FRANKIE F
IPC分类号： G06F13/00 , G11C16/06
CPC分类号： G11C16/10 , G11C7/16 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C27/005
摘要： Memory devices (101/301) adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices (101/301) includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices (101/301) includes generating an analog data signal indicative of a threshold voltage of a target memory cell. This analog signal may then be processed to convert it to a digital representation of the individual bits of the bit pattern represented by the analog signal. Such memory devices (101/301) may be incorporated into bulk storage devices (300), and may utilize form factors and communication protocols of hard disk drives (HDDs) and other traditional bulk storage devices for transparent replacement of such traditional bulk storage devices in electronic systems.
摘要翻译：适于处理和产生表示两个或更多位信息的数据值的模拟数据信号的存储器件（101/301）有助于相对于器件处理和仅产生指示各个位的二进制数据信号的数据传输速率的增加。这种存储器件（101/301）的编程包括对表示所需位图案的目标阈值电压范围的编程。读取这样的存储器件（101/301）包括产生指示目标存储器单元的阈值电压的模拟数据信号。然后可以处理该模拟信号以将其转换为由模拟信号表示的位模式的各个位的数字表示。这种存储设备（101/301）可以并入大容量存储设备（300）中，并且可以利用硬盘驱动器（HDD）和其他传统大容量存储设备的形式因素和通信协议来透明地更换这样的传统大容量存储设备电子系统。

9. 发明申请

WO2008094899A2 MEMORY DEVICE ARCHITECTURES AND OPERATION 审中-公开
标题翻译：存储器设备结构和操作
公开(公告)号：WO2008094899A2
公开(公告)日：2008-08-07
申请号：PCT/US2008052299
申请日：2008-01-29
申请人： MICRON TECHNOLOGY INC , ROOHPARVAR FRANKIE F
发明人： ROOHPARVAR FRANKIE F
IPC分类号： G11C16/16
CPC分类号： G11C16/06 , G06F12/0246 , G06F12/04 , G06F2212/2022 , G11C16/16 , G11C19/0858
摘要： Non- volatile memory devices (100, 610) logically organized to have erase blocks of at least two different sizes provide for concurrent erasure of multiple physical blocks (340) of memory cells (208, 308), while providing for individual selection of those physical blocks (340) for read and program operations, hi this manner, data expected to require frequent updating can be stored in locations corresponding to first erase blocks having a first size while data expected to require relatively infrequent updating can be stored in locations corresponding to second erase blocks larger than the first erase blocks. Storing data expected to require relatively more frequent updating in smaller logical memory blocks facilitates a reduction in unnecessary erasing of memory cells (208, 308). In addition, by providing for larger logical memory blocks for storing data expected to require relatively less frequent updating, efficiencies can be obtained in erasing larger quantities of memory cells (208, 308) concurrently.
摘要翻译：在逻辑上组织成具有至少两种不同尺寸的擦除块的非易失性存储器装置（100,610）提供存储器单元（208,308）的多个物理块（340）的同时擦除，同时提供对那些物理用于读取和编程操作的块（340）。以这种方式，期望需要频繁更新的数据可被存储在与具有第一大小的第一擦除块对应的位置中，而期望需要相对不常见的更新的数据可被存储在与第二擦除大于第一擦除块的块。存储期望在更小的逻辑存储器块中需要相对更频繁地更新的数据有助于减少存储器单元的不必要的擦除（208,308）。另外，通过提供更大的逻辑存储块来存储预期需要相对较少频繁更新的数据，可同时擦除更大量的存储单元（208,308）中获得效率。

10. 发明申请

WO2010033975A3 PROGRAMMING A MEMORY DEVICE TO INCREASE DATA RELIABILITY 审中-公开
标题翻译：编程存储器件提高数据可靠性
公开(公告)号：WO2010033975A3
公开(公告)日：2010-05-14
申请号：PCT/US2009057810
申请日：2009-09-22
申请人： MICRON TECHNOLOGY INC , ROOHPARVAR FRANKIE F
发明人： ROOHPARVAR FRANKIE F
IPC分类号： G11C16/34 , G11C16/02 , G11C16/10
CPC分类号： G06F12/0246 , G06F12/00 , G11C16/0483 , G11C16/10
摘要： Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group of memory cells of the array having a relative reliability corresponding to the target reliability.
摘要翻译：公开了用于编程存储器阵列，存储器件和存储器系统的方法。在一种这样的方法中，确定要编程的数据的目标可靠性。确定存储器阵列的不同存储单元组的相对可靠性。将数据编程到具有与目标可靠性相对应的相对可靠性的阵列的存储器单元组中。

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