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1. 发明申请

WO2011152858A2 OXIDE BASED MEMORY 审中-公开
标题翻译：基于氧化物的存储器
公开(公告)号：WO2011152858A2
公开(公告)日：2011-12-08
申请号：PCT/US2011/000971
申请日：2011-05-27
申请人： MICRON TECHNOLOGY, INC. , RAMASWAMY, D., V., Nirmal , SANDHU, Gurtej, S.
发明人： RAMASWAMY, D., V., Nirmal , SANDHU, Gurtej, S.
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： G11C13/0007 , G11C2213/55 , G11C2213/56 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1616
摘要： Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.
摘要翻译：本文描述了与基于氧化物的存储器相关联的方法，设备和系统。在一个或多个实施例中，形成基于氧化物的存储单元的方法包括形成第一电极，形成隧道势垒，其中隧道势垒的第一部分包括第一材料，隧道势垒的第二部分包括第二材料，形成氧源，形成第二电极。

2. 发明申请

WO2013142713A1 MEMORY CELLS, SEMICONDUCTOR DEVICE STRUCTURES, SYSTEMS INCLUDING SUCH CELLS, AND METHODS OF FABRICATION 审中-公开
标题翻译：记忆细胞，半导体器件结构，包括这些细胞的系统以及制造方法
公开(公告)号：WO2013142713A1
公开(公告)日：2013-09-26
申请号：PCT/US2013/033344
申请日：2013-03-21
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej, S. , KINNEY, Wayne, I.
发明人： SANDHU, Gurtej, S. , KINNEY, Wayne, I.
IPC分类号： G11C11/15 , H01L27/115 , H01L21/8247
CPC分类号： H01L43/08 , G11C11/15 , G11C11/161 , H01F10/1936 , H01F10/3286 , H01F10/329 , H01L27/228 , H01L43/02 , H01L43/12
摘要： Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells.
摘要翻译：公开了包括具有自由区域的单元芯的存储单元。自由区域表现出影响细胞核心内的磁化取向的应变。应力结构可能对细胞芯的至少一部分施加应力以实现自由区的应变状态。还公开了包括这种存储单元的半导体器件结构和系统以及用于形成这种存储单元的方法。

3. 发明申请

WO2013015935A2 METHODS OF FORMING GRAPHENE-CONTAINING SWITCHES 审中-公开
标题翻译：形成含石墨开关的方法
公开(公告)号：WO2013015935A2
公开(公告)日：2013-01-31
申请号：PCT/US2012/044484
申请日：2012-06-27
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej, S.
发明人： SANDHU, Gurtej, S.
IPC分类号： H01L27/02
CPC分类号： H01L21/768 , H01L23/525 , H01L23/53276 , H01L29/0665 , H01L29/0676 , H01L29/1606 , H01L29/66022 , H01L29/66742 , H01L29/7788 , H01L29/78642 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive structure may be formed to extend upwardly from the bottom electrode. Dielectric material may be formed along a sidewall of the first electrically conductive structure, while leaving a portion of the bottom electrode exposed. A graphene structure may be formed to be electrically coupled with the exposed portion of the bottom electrode. A second electrically conductive structure may be formed on an opposing side of the graphene structure from the first electrically conductive structure. A top electrode may be formed over the graphene structure and electrically coupled with the second electrically conductive structure. The first and second electrically conductive structures may be configured to provide an electric field across the graphene structure.
摘要翻译：一些实施方案包括形成含石墨烯开关的方法。底部电极可以形成在基底上，并且第一导电结构可以形成为从底部电极向上延伸。电介质材料可以沿着第一导电结构的侧壁形成，同时使底部电极的一部分暴露。石墨烯结构可以形成为与底部电极的暴露部分电耦合。第二导电结构可以形成在石墨烯结构的与第一导电结构相反的一侧上。顶部电极可以形成在石墨烯结构上并且与第二导电结构电耦合。第一和第二导电结构可以被配置成提供穿过石墨烯结构的电场。

4. 发明申请

WO2011093995A2 GCIB-TREATED RESISTIVE DEVICE 审中-公开
标题翻译： GCIB处理电阻器件
公开(公告)号：WO2011093995A2
公开(公告)日：2011-08-04
申请号：PCT/US2011/000134
申请日：2011-01-25
申请人： MICRON TECHNOLOGY, INC. , SMYTHE III, John, A. , SANDHU, Gurtej, S.
发明人： SMYTHE III, John, A. , SANDHU, Gurtej, S.
IPC分类号： H01L27/105 , H01L21/8247
CPC分类号： H01L45/165 , G11C13/0007 , G11C2213/56 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1641 , H01L45/1683
摘要： The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.
摘要翻译：本公开包括GCIB处理的电阻性装置，利用GCIB处理的电阻性装置（例如，作为开关，存储器单元）的装置以及用于形成经GCIB处理的电阻装置的方法。形成GCIB处理的电阻性器件的一种方法包括形成下电极，并在下电极上形成氧化物材料。将氧化物材料暴露于气体簇离子束（GCIB），直到氧化物材料的第一部分的电阻相对于氧化物材料的第二部分的电阻发生变化。在第一部分上形成上电极。

5. 发明申请

WO2010096094A1 MEMORY DEVICES AND FORMATION METHODS 审中-公开
标题翻译：记忆装置和形成方法
公开(公告)号：WO2010096094A1
公开(公告)日：2010-08-26
申请号：PCT/US2009/057017
申请日：2009-09-15
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun , SANDHU, Gurtej, S.
发明人： LIU, Jun , SANDHU, Gurtej, S.
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/02225 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/16
摘要： A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state -changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.
摘要翻译：一种方法包括在具有含金属的导电互连的集成电路上形成电绝缘体材料，并激活衬底的半导体材料中的掺杂剂以提供掺杂区域。掺杂区域提供相反导电类型的结。在激活掺杂剂之后，衬底被结合到绝缘体材料上，并且至少部分衬底在与绝缘体材料接合的情况下被去除。在去除之后，形成具有字线，存取二极管，含有硫族化物相变材料的状态可变存储元件和全部电连接的位线的存储单元，该存储二极管包含接合点作为pn结。存储器件包括绝缘体材料上的粘附材料并将字线连接到绝缘体材料。

6. 发明申请

WO2010065249A2 METHODS OF FABRICATING SUBSTRATES 审中-公开
标题翻译：制作基板的方法
公开(公告)号：WO2010065249A2
公开(公告)日：2010-06-10
申请号：PCT/US2009/063978
申请日：2009-11-11
申请人： MICRON TECHNOLOGY, INC. , SILLS, Scott , SANDHU, Gurtej, S. , DEVILLIERS, Anton
发明人： SILLS, Scott , SANDHU, Gurtej, S. , DEVILLIERS, Anton
IPC分类号： H01L21/027
CPC分类号： H01L21/31138 , G03F7/0035 , H01L21/0273 , H01L21/0337 , H01L21/0338
摘要： A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.
摘要翻译：制造衬底的方法包括在衬底上形成间隔开的第一特征和间隔开的第二特征。第一和第二特征彼此交替并彼此间隔开。间隔开的第二特征的宽度被横向修整到比间隔开的第一特征的宽度的任何横向修剪更大的程度，同时横向地修剪间隔开的第二特征的宽度。在第二特征的横向修剪之后，间隔物形成在间隔开的第一特征的侧壁上并且在间隔开的第二特征的侧壁上。间隔物与间隔开的第一特征和间隔开的第二特征的间隔物具有不同的组成。在形成间隔物之后，从衬底去除间隔开的第一特征和间隔开的第二特征。通过包括间隔物的掩模图案处理衬底。公开了其它实施例。

7. 发明申请

WO2010062645A3 METHODS OF FORMING DIODES 审中-公开
公开(公告)号：WO2010062645A3
公开(公告)日：2010-06-03
申请号：PCT/US2009/062358
申请日：2009-10-28
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej, S. , SRINIVASAN, Bhaskar
发明人： SANDHU, Gurtej, S. , SRINIVASAN, Bhaskar
IPC分类号： H01L29/861
摘要： Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

8. 发明申请

WO2009091448A1 SEMICONDUCTOR CONSTRUCTIONS, NAND UNIT CELLS, METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS, AND METHODS OF FORMING NAND UNIT CELLS 审中-公开
标题翻译：半导体结构，NAND单元，形成半导体结构的方法和形成NAND单元电池的方法
公开(公告)号：WO2009091448A1
公开(公告)日：2009-07-23
申请号：PCT/US2008/084683
申请日：2008-11-25
申请人： MICRON TECHNOLOGY, INC. , RAMASWAMY, D.V., Nirmal , SANDHU, Gurtej, S.
发明人： RAMASWAMY, D.V., Nirmal , SANDHU, Gurtej, S.
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11582 , G11C16/0483 , H01L21/8239 , H01L27/0738 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/42328 , H01L29/42348 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Some embodiments include methods of forming semiconductor constructions Alternating layers of n-type doped material and p-type doped material may be formed The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric Alternating layers of insulative material and conductive control gate material may be formed within the lined openings Some embodiments include methods of forming NAND unit cells Columns of alternating n-type material and p-type material may be formed The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric Alternating layers of insulative material and conductive control gate material may be formed between the lined columns Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.
摘要翻译：一些实施例包括形成半导体结构的方法可以形成n型掺杂材料和p型掺杂材料的交替层。交替层可以被图案化成通过开口彼此间隔开的多个垂直列。开口可以是衬里隧道电介质，电荷存储材料和阻挡介质绝缘材料和导电控制栅极材料的交替层可以在衬里开口内形成。一些实施例包括形成NAND单元电池的方法交替的n型材料和p型材料的列可以可以形成列可以衬有隧道电介质层，电荷存储材料层和阻挡介电层在衬里柱之间可以形成绝缘材料和导电控制栅极材料的交替层。一些实施例包括半导体结构，并且一些实施例包括NAND单元单元。

9. 发明申请

WO2012021237A1 MEMORY CELLS, NON-VOLATILE MEMORY ARRAYS, METHODS OF OPERATING MEMORY CELLS, METHODS OF READING TO AND WRITING A MEMORY CELL, AND METHODS OF PROGRAMMING A MEMORY CELL 审中-公开
标题翻译：存储器细胞，非易失性存储器阵列，操作存储器单元的方法，读取和写入存储器单元的方法以及编程存储器单元的方法
公开(公告)号：WO2012021237A1
公开(公告)日：2012-02-16
申请号：PCT/US2011/043504
申请日：2011-07-11
申请人： MICRON TECHNOLOGY, INC. , SRINIVASAN, Bhaskar , SANDHU, Gurtej, S.
发明人： SRINIVASAN, Bhaskar , SANDHU, Gurtej, S.
IPC分类号： G11C16/12 , G11C16/02
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/12 , G11C2213/32 , G11C2213/34 , G11C2213/52 , G11C2213/56 , G11C2213/77 , H01L27/101 , H01L45/08 , H01L45/085 , H01L45/1206
摘要： In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between. The material has first and second lateral regions of different composition relative one another. One of the first and second lateral regions is received along one of two laterally opposing edges of the material. Another of the first and second lateral regions is received along the other of said two laterally opposing edges of the material. At least one of the first and second lateral regions is capable of being repeatedly programmed to at least two different resistance states. Other aspects and implementations are disclosed.
摘要翻译：一方面，操作存储单元的方法包括使用不同的电极来改变存储器单元的编程状态，而不是用于读取存储器单元的编程状态。在一个方面，存储单元包括第一和第二相对电极，其间具有接收在其间的材料。该材料具有彼此不同组成的第一和第二横向区域。第一和第二横向区域中的一个沿着材料的两个横向相对的边缘中的一个被接收。第一和第二横向区域中的另一个沿着材料的所述两个横向相对的边缘中的另一个被容纳。第一和第二横向区域中的至少一个能够被重复编程至至少两个不同的阻力状态。公开了其他方面和实现。

10. 发明申请

WO2012008989A2 FORMING MEMORY USING HIGH POWER IMPULSE MAGNETRON SPUTTERING 审中-公开
标题翻译：用大功率脉冲磁控溅射成形记忆
公开(公告)号：WO2012008989A2
公开(公告)日：2012-01-19
申请号：PCT/US2011/001100
申请日：2011-06-21
申请人： MICRON TECHNOLOGY, INC. , HU, Yongjun, Jeff , MCTEER, Everett, A. , SMYTHE, John, A. III , SANDHU, Gurtej, S.
发明人： HU, Yongjun, Jeff , MCTEER, Everett, A. , SMYTHE, John, A. III , SANDHU, Gurtej, S.
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/203
CPC分类号： H01J37/3467 , C23C14/08 , C23C14/082 , C23C14/088 , C23C14/3407 , C23C14/3485 , C23C14/35 , H01J37/3417 , H01J37/3426 , H01J2237/3322 , H01L21/02192 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron sputtering (HIPIMS), wherein the resistive memory material is formed on the structure in an environment having a temperature of approximately 400 degrees Celsius or less.
摘要翻译：这里描述了使用高功率脉冲磁控管溅射形成存储器。一个或多个方法实施例包括使用高功率脉冲磁控溅射（HIPIMS）在结构上形成电阻式存储器材料，其中电阻式存储器材料在具有大约400摄氏度或更低的温度的环境中的结构上形成。 p>

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