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1. 发明申请

WO2010062645A3 METHODS OF FORMING DIODES 审中-公开
公开(公告)号：WO2010062645A3
公开(公告)日：2010-06-03
申请号：PCT/US2009/062358
申请日：2009-10-28
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej, S. , SRINIVASAN, Bhaskar
发明人： SANDHU, Gurtej, S. , SRINIVASAN, Bhaskar
IPC分类号： H01L29/861
摘要： Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

2. 发明申请

WO2012021237A1 MEMORY CELLS, NON-VOLATILE MEMORY ARRAYS, METHODS OF OPERATING MEMORY CELLS, METHODS OF READING TO AND WRITING A MEMORY CELL, AND METHODS OF PROGRAMMING A MEMORY CELL 审中-公开
标题翻译：存储器细胞，非易失性存储器阵列，操作存储器单元的方法，读取和写入存储器单元的方法以及编程存储器单元的方法
公开(公告)号：WO2012021237A1
公开(公告)日：2012-02-16
申请号：PCT/US2011/043504
申请日：2011-07-11
申请人： MICRON TECHNOLOGY, INC. , SRINIVASAN, Bhaskar , SANDHU, Gurtej, S.
发明人： SRINIVASAN, Bhaskar , SANDHU, Gurtej, S.
IPC分类号： G11C16/12 , G11C16/02
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/12 , G11C2213/32 , G11C2213/34 , G11C2213/52 , G11C2213/56 , G11C2213/77 , H01L27/101 , H01L45/08 , H01L45/085 , H01L45/1206
摘要： In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between. The material has first and second lateral regions of different composition relative one another. One of the first and second lateral regions is received along one of two laterally opposing edges of the material. Another of the first and second lateral regions is received along the other of said two laterally opposing edges of the material. At least one of the first and second lateral regions is capable of being repeatedly programmed to at least two different resistance states. Other aspects and implementations are disclosed.
摘要翻译：一方面，操作存储单元的方法包括使用不同的电极来改变存储器单元的编程状态，而不是用于读取存储器单元的编程状态。在一个方面，存储单元包括第一和第二相对电极，其间具有接收在其间的材料。该材料具有彼此不同组成的第一和第二横向区域。第一和第二横向区域中的一个沿着材料的两个横向相对的边缘中的一个被接收。第一和第二横向区域中的另一个沿着材料的所述两个横向相对的边缘中的另一个被容纳。第一和第二横向区域中的至少一个能够被重复编程至至少两个不同的阻力状态。公开了其他方面和实现。

3. 发明申请

WO2011037703A2 METHODS OF READING AND USING MEMORY CELLS 审中-公开
标题翻译：阅读和使用记忆细胞的方法
公开(公告)号：WO2011037703A2
公开(公告)日：2011-03-31
申请号：PCT/US2010/045856
申请日：2010-08-18
申请人： MICRON TECHNOLOGY, INC. , SRINIVASAN, Bhaskar , SANDHU, Gurtej, S.
发明人： SRINIVASAN, Bhaskar , SANDHU, Gurtej, S.
IPC分类号： G11C16/26 , G11C16/32 , G11C16/10
CPC分类号： G11C13/004 , G11C13/0002 , G11C13/0007 , G11C13/0061 , G11C2013/0052 , G11C2213/72
摘要： Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration to be sufficient for the write operation. In some embodiments, the pulse utilized for the reading may have an absolute value of voltage that is greater than or equal to the voltage utilized for the write operation. In some embodiments, the memory cells may comprise non-ohmic devices; such as memristors and diodes.
摘要翻译：一些实施例包括读取存储器单元的方法。存储器单元具有仅在足够的时间长度施加足够的绝对值的电压时发生的写入操作; 并且读取是用太短于持续时间的脉冲来进行的，以足以用于写入操作。在一些实施例中，用于读取的脉冲可以具有大于或等于用于写入操作的电压的绝对值。在一些实施例中，存储器单元可以包括非欧姆器件; 如忆阻器和二极管。

4. 发明申请

WO2010059451A2 SELECT DEVICES INCLUDING AN OPEN VOLUME, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS FOR FORMING SAME 审中-公开
标题翻译：包括开放体积的选择装置，包括其的记忆装置和系统及其形成方法
公开(公告)号：WO2010059451A2
公开(公告)日：2010-05-27
申请号：PCT/US2009/063761
申请日：2009-11-09
申请人： MICRON TECHNOLOGY, INC. , SRINIVASAN, Bhaskar , SANDHU, Gurtej, S.
发明人： SRINIVASAN, Bhaskar , SANDHU, Gurtej, S.
IPC分类号： H01L29/861
CPC分类号： H01L29/88 , H01L21/3205 , H01L27/1021 , Y10S438/957
摘要： Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select device may comprise, for example, a metal insulator insulator metal (MIIM) device. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.
摘要翻译：公开了包括用作具有低介电常数的高带隙材料的开放体积的装置。开放体积可以在选择装置中提供更非线性，不对称的I-V曲线和增强的整流行为。选择装置可以包括例如金属绝缘体绝缘金属（MIIM）装置。可以使用各种方法来形成包括这种选择装置的选择装置和存储器系统。存储器件和电子系统包括这样的选择器件。

5. 发明申请

WO2009154886A2 DIODES, AND METHODS OF FORMING DIODES 审中-公开
标题翻译：二极体和形成二极体的方法
公开(公告)号：WO2009154886A2
公开(公告)日：2009-12-23
申请号：PCT/US2009/042540
申请日：2009-05-01
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej, S. , SRINIVASAN, Bhaskar
发明人： SANDHU, Gurtej, S. , SRINIVASAN, Bhaskar
IPC分类号： H01L29/861
CPC分类号： H01L45/00 , Y10S257/91 , Y10S438/90 , Y10S438/902 , Y10S438/983
摘要： Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.
摘要翻译：一些实施例包括形成二极管的方法。所述方法可以包括氧化导电电极的上表面以在导电电极上形成氧化物层。在一些实施方案中，所述方法可包括在导电电极上形成可氧化材料，以及随后氧化可氧化材料以在导电电极上形成氧化物层。在一些实施例中，所述方法可包括在导电电极上形成金属卤化物层。一些实施例包括在一对二极管电极之间包含金属卤化物层的二极管。

6. 发明申请

WO2012030380A2 MEMORY CELL STRUCTURES AND METHODS 审中-公开
标题翻译：记忆细胞结构和方法
公开(公告)号：WO2012030380A2
公开(公告)日：2012-03-08
申请号：PCT/US2011/001484
申请日：2011-08-24
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej, S. , SRINIVASAN, Bhaskar
发明人： SANDHU, Gurtej, S. , SRINIVASAN, Bhaskar
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： G11C16/0416 , G11C16/0483
摘要： Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positioned between a source region and a drain region, and a first electrode of a diode coupled to the charge storage node.
摘要翻译：这里描述了存储单元结构和方法。一个或多个存储器单元包括具有电荷存储节点的晶体管，位于电荷存储节点和晶体管的沟道区域之间的电介质材料，沟道区域位于源极区域和漏极区域之间，以及第一电极二极管耦合到电荷存储节点。

7. 发明申请

WO2013142713A1 MEMORY CELLS, SEMICONDUCTOR DEVICE STRUCTURES, SYSTEMS INCLUDING SUCH CELLS, AND METHODS OF FABRICATION 审中-公开
标题翻译：记忆细胞，半导体器件结构，包括这些细胞的系统以及制造方法
公开(公告)号：WO2013142713A1
公开(公告)日：2013-09-26
申请号：PCT/US2013/033344
申请日：2013-03-21
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej, S. , KINNEY, Wayne, I.
发明人： SANDHU, Gurtej, S. , KINNEY, Wayne, I.
IPC分类号： G11C11/15 , H01L27/115 , H01L21/8247
CPC分类号： H01L43/08 , G11C11/15 , G11C11/161 , H01F10/1936 , H01F10/3286 , H01F10/329 , H01L27/228 , H01L43/02 , H01L43/12
摘要： Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells.
摘要翻译：公开了包括具有自由区域的单元芯的存储单元。自由区域表现出影响细胞核心内的磁化取向的应变。应力结构可能对细胞芯的至少一部分施加应力以实现自由区的应变状态。还公开了包括这种存储单元的半导体器件结构和系统以及用于形成这种存储单元的方法。

8. 发明申请

WO2013015935A2 METHODS OF FORMING GRAPHENE-CONTAINING SWITCHES 审中-公开
标题翻译：形成含石墨开关的方法
公开(公告)号：WO2013015935A2
公开(公告)日：2013-01-31
申请号：PCT/US2012/044484
申请日：2012-06-27
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej, S.
发明人： SANDHU, Gurtej, S.
IPC分类号： H01L27/02
CPC分类号： H01L21/768 , H01L23/525 , H01L23/53276 , H01L29/0665 , H01L29/0676 , H01L29/1606 , H01L29/66022 , H01L29/66742 , H01L29/7788 , H01L29/78642 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive structure may be formed to extend upwardly from the bottom electrode. Dielectric material may be formed along a sidewall of the first electrically conductive structure, while leaving a portion of the bottom electrode exposed. A graphene structure may be formed to be electrically coupled with the exposed portion of the bottom electrode. A second electrically conductive structure may be formed on an opposing side of the graphene structure from the first electrically conductive structure. A top electrode may be formed over the graphene structure and electrically coupled with the second electrically conductive structure. The first and second electrically conductive structures may be configured to provide an electric field across the graphene structure.
摘要翻译：一些实施方案包括形成含石墨烯开关的方法。底部电极可以形成在基底上，并且第一导电结构可以形成为从底部电极向上延伸。电介质材料可以沿着第一导电结构的侧壁形成，同时使底部电极的一部分暴露。石墨烯结构可以形成为与底部电极的暴露部分电耦合。第二导电结构可以形成在石墨烯结构的与第一导电结构相反的一侧上。顶部电极可以形成在石墨烯结构上并且与第二导电结构电耦合。第一和第二导电结构可以被配置成提供穿过石墨烯结构的电场。

9. 发明申请

WO2011093995A2 GCIB-TREATED RESISTIVE DEVICE 审中-公开
标题翻译： GCIB处理电阻器件
公开(公告)号：WO2011093995A2
公开(公告)日：2011-08-04
申请号：PCT/US2011/000134
申请日：2011-01-25
申请人： MICRON TECHNOLOGY, INC. , SMYTHE III, John, A. , SANDHU, Gurtej, S.
发明人： SMYTHE III, John, A. , SANDHU, Gurtej, S.
IPC分类号： H01L27/105 , H01L21/8247
CPC分类号： H01L45/165 , G11C13/0007 , G11C2213/56 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1641 , H01L45/1683
摘要： The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.
摘要翻译：本公开包括GCIB处理的电阻性装置，利用GCIB处理的电阻性装置（例如，作为开关，存储器单元）的装置以及用于形成经GCIB处理的电阻装置的方法。形成GCIB处理的电阻性器件的一种方法包括形成下电极，并在下电极上形成氧化物材料。将氧化物材料暴露于气体簇离子束（GCIB），直到氧化物材料的第一部分的电阻相对于氧化物材料的第二部分的电阻发生变化。在第一部分上形成上电极。

10. 发明申请

WO2010096094A1 MEMORY DEVICES AND FORMATION METHODS 审中-公开
标题翻译：记忆装置和形成方法
公开(公告)号：WO2010096094A1
公开(公告)日：2010-08-26
申请号：PCT/US2009/057017
申请日：2009-09-15
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun , SANDHU, Gurtej, S.
发明人： LIU, Jun , SANDHU, Gurtej, S.
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/02225 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/16
摘要： A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state -changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.
摘要翻译：一种方法包括在具有含金属的导电互连的集成电路上形成电绝缘体材料，并激活衬底的半导体材料中的掺杂剂以提供掺杂区域。掺杂区域提供相反导电类型的结。在激活掺杂剂之后，衬底被结合到绝缘体材料上，并且至少部分衬底在与绝缘体材料接合的情况下被去除。在去除之后，形成具有字线，存取二极管，含有硫族化物相变材料的状态可变存储元件和全部电连接的位线的存储单元，该存储二极管包含接合点作为pn结。存储器件包括绝缘体材料上的粘附材料并将字线连接到绝缘体材料。

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