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1. 发明申请

WO2016014288A1 APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY 审中-公开
标题翻译：用于同时访问存储器的不同存储器的设备和方法
公开(公告)号：WO2016014288A1
公开(公告)日：2016-01-28
申请号：PCT/US2015/040346
申请日：2015-07-14
申请人： MICRON TECHNOLOGY, INC.
发明人： VALI, Tommaso , XOTTA, Andrea, Giovanni , SICILIANI, Umberto , DESANTIS, Luca , INCARNATI, Michele
IPC分类号： G11C16/08 , G11C16/26
CPC分类号： G06F12/0646 , G06F12/023 , G06F12/0238 , G06F2212/1016 , G06F2212/251 , G06F2212/7208
摘要： Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.
摘要翻译：本文公开了同时访问不同存储器平面的装置和方法。示例性设备可以包括与被配置为维护与多个存储器命令和地址对中的每一个相关联的相应信息的队列相关联的控制器。控制器被配置为基于由队列维护的信息从多个存储器命令和地址对中选择一组存储器命令和地址对。该示例设备还包括被配置为接收该组存储器命令和地址对的存储器。存储器被配置为同时执行与该组存储器命令和地址对相关联的存储器访问操作。

2. 发明申请

WO2019045913A1 DETERMINING DATA STATES OF MEMORY CELLS 审中-公开
公开(公告)号：WO2019045913A1
公开(公告)日：2019-03-07
申请号：PCT/US2018/043624
申请日：2018-07-25
申请人： MICRON TECHNOLOGY, INC.
发明人： VALI, Tommaso , DE SANTIS, Luca , GHODSI, Ramin
IPC分类号： G11C16/10 , G11C16/26 , G11C16/34
摘要： Methods of operating a memory include determining a respective raw data value for each memory cell of a plurality of memory cells; determining the numbers of memory cells of a first subset of the plurality of memory cells having each raw data value as their respective raw data value; determining a respective raw data values representative of transition between each pair of adjacent data states responsive to the determined numbers of memory cells of the first subset of the plurality of memory cells for each raw data value; and determining a respective data state of the plurality of data states for each memory cell of a second subset of the plurality of memory cells responsive to its respective raw data value and to the determined raw data values representative of the transitions between adjacent data states.

3. 发明申请

WO2008121351A1 NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING WITH MORE THAN TWO VERIFY VOLTAGES PER LEVEL 审中-公开
标题翻译：非易失性多重存储器单元编程，具有超过每级的两个验证电压
公开(公告)号：WO2008121351A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/004114
申请日：2008-03-28
申请人： MICRON TECHNOLOGY, INC. , MOSCHIANO, Violante , SANTIN, Giovanni , VALI, Tommaso , ROSSINI, Massimo
发明人： MOSCHIANO, Violante , SANTIN, Giovanni , VALI, Tommaso , ROSSINI, Massimo
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3404 , G11C16/3486 , G11C2211/5621 , G11C2211/5625
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY.
摘要翻译：本公开的实施例提供用于编程多电平非易失性多电平存储器单元的方法，设备，模块和系统。一种方法包括增加用于多个存储器单元中的每一个的阈值电压（Vt），直到Vt达到与多个程序状态中的程序状态相对应的验证电压（VFY）。该方法包括确定每个单元的Vt是否已经达到与编程状态相关联的预验证电压（PVFY），选择性地偏置与Vt已经达到PVFY的那些单元耦合的位线，将PVFY调整到不同的电平并且选择性地偏置与Vt已经达到调整后的PVFY的单元相连的位线，其中PVFY和调整后的PVFY小于VFY。

4. 发明申请

WO2020139615A1 MEMORY CELLS CONFIGURED TO GENERATE WEIGHTED INPUTS FOR NEURAL NETWORKS 审中-公开
公开(公告)号：WO2020139615A1
公开(公告)日：2020-07-02
申请号：PCT/US2019/066740
申请日：2019-12-17
申请人： MICRON TECHNOLOGY, INC.
发明人： MINUCCI, Umberto , VALI, Tommaso , IRRERA, Fernanda , DE SANTIS, Luca
IPC分类号： G11C11/54 , G11C16/10 , G06N3/063
摘要： A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.

5. 发明申请

WO2013032928A1 THRESHOLD VOLTAGE COMPENSATION IN A MEMORY 审中-公开
标题翻译：存储器中的阈值电压补偿
公开(公告)号：WO2013032928A1
公开(公告)日：2013-03-07
申请号：PCT/US2012/052333
申请日：2012-08-24
申请人： MICRON TECHNOLOGY, INC. , MOSCHIANO, Violante , VALI, Tommaso , NASO, Giovanni , SARIN, Vishal , RADKE, William Henry , PEKNY, Theodore T.
发明人： MOSCHIANO, Violante , VALI, Tommaso , NASO, Giovanni , SARIN, Vishal , RADKE, William Henry , PEKNY, Theodore T.
IPC分类号： G11C16/34 , G11C16/26
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed "aggressor" memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

6. 发明申请

WO2007095217A1 SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：多级单元存储器中的单锁数据电路
公开(公告)号：WO2007095217A1
公开(公告)日：2007-08-23
申请号：PCT/US2007/003749
申请日：2007-02-14
申请人： MICRON TECHNOLOGY, INC. , VALI, Tommaso , SANTIN, Giovanni , INCARNATI, Michele
发明人： VALI, Tommaso , SANTIN, Giovanni , INCARNATI, Michele
IPC分类号： G11C16/26 , G11C11/56 , G11C16/10
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5642
摘要： A single latch, circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存器电路耦合到多级单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

7. 发明申请

WO2006138413A1 SELECTIVE SLOW PROGRAMMING CONVERGENCE IN A FLASH MEMORY DEVICE 审中-公开
标题翻译：闪存存储器中的选择性慢速编程融合
公开(公告)号：WO2006138413A1
公开(公告)日：2006-12-28
申请号：PCT/US2006/023217
申请日：2006-06-13
申请人： MICRON TECHNOLOGY, INC. , INCARNATI, Michele , SANTIN, Giovanni , VALI, Tommaso
发明人： INCARNATI, Michele , SANTIN, Giovanni , VALI, Tommaso
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3404 , G11C2211/5621
摘要： A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre- verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre- verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.
摘要翻译：多个存储器单元被编程，其中增加的编程脉冲被施加到存储器单元耦合到的字线。在每个脉冲之后，验证操作确定每个单元的阈值电压。当阈值电压达到预验证阈值时，只有连接到该特定单元的位线被中间电压偏置，该中间电压降低了单元的Vt的变化。其他细胞继续按其正常速度进行编程。当每个单元的Vt达到预验证电平时，它被中间电压偏置。当它们的阈值电压达到验证电压阈值时，所有位线都被抑制电压偏置。

8. 发明申请

WO2015119793A1 MEMORY SYSTEMS AND MEMORY CONTROL METHODS 审中-公开
标题翻译：存储器系统和存储器控制方法
公开(公告)号：WO2015119793A1
公开(公告)日：2015-08-13
申请号：PCT/US2015/012735
申请日：2015-01-23
申请人： MICRON TECHNOLOGY, INC.
发明人： SMANIOTTO, Andrea , SICILIANI, Umberto , VALI, Tommaso , DI-FRANCESCO, Walter , MOSCHIANO, Violante , SMANIOTTO, Andrea
IPC分类号： G06F12/02
CPC分类号： G06F9/328 , G06F9/321
摘要： Memory systems and memory control methods are described. According to one aspect, a memory system includes a plurality of memory cells individually configured to store data, program memory configured to store a plurality of first executable instructions which are ordered according to a first instruction sequence and a plurality of second executable instructions which are ordered according to a second instruction sequence, substitution circuitry configured to replace one of the first executable instructions with a substitute executable instruction, and a control unit configured to execute the first and second executable instructions to control reading and writing of the data with respect to the memory, wherein the control unit is configured to execute the first executable instructions according to the first instruction sequence, to execute the substitute executable instruction after the execution of the first executable instructions, and to execute the second executable instructions according to the second instruction sequence as a result of execution of the substitute executable instruction.
摘要翻译：描述了存储器系统和存储器控制方法。根据一个方面，一种存储器系统包括单独配置为存储数据的多个存储器单元，被配置为存储根据第一指令序列排序的多个第一可执行指令的程序存储器和被排序的多个第二可执行指令根据第二指令序列，替代电路被配置为用替代可执行指令来替换第一可执行指令之一，以及控制单元，被配置为执行第一和第二可执行指令以控制相对于存储器的数据的读取和写入其中，所述控制单元被配置为根据所述第一指令序列执行所述第一可执行指令，以在执行所述第一可执行指令之后执行所述替代可执行指令，并且根据所述第二指令序列执行所述第二可执行指令作为的结果执行替代可执行指令。

9. 发明申请

WO2013155179A1 DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS 审中-公开
标题翻译：确定记忆细胞组合的软数据
公开(公告)号：WO2013155179A1
公开(公告)日：2013-10-17
申请号：PCT/US2013/035969
申请日：2013-04-10
申请人： MICRON TECHNOLOGY, INC.
发明人： MOSCHIANO, Violante , VALI, Tommaso , HAWES, Mark A.
IPC分类号： G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells, wherein the array includes a first memory cell and a second memory cell, wherein the first and second memory cells are each programmable to one of a number of program states, and wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states. A number of embodiments also include a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and determine soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell.
摘要翻译：本公开包括用于确定存储器单元的组合的软数据的装置和方法。多个实施例包括存储器单元的阵列，其中阵列包括第一存储单元和第二存储单元，其中第一和第二存储单元可编程为多个程序状态之一，并且其中第一和第二存储器单元的程序状态对应于多个数据状态之一。多个实施例还包括耦合到阵列的缓冲器和/或控制器，并且被配置为确定与第一和第二存储器单元的程序状态相关联的软数据，并且确定与数据状态相关联的软数据，该数据状态对应于至少部分地基于与第一存储器单元的程序状态相关联的软数据和与第二存储器单元的程序状态相关联的软数据的第一和第二存储器单元的程序状态。

10. 发明申请

WO2013025342A1 MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE 审中-公开
标题翻译：用于存储器件的存储器件和配置方法
公开(公告)号：WO2013025342A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/048975
申请日：2012-07-31
申请人： MICRON TECHNOLOGY, INC. , RADKE, William H. , VALI, Tommaso , INCARNATI, Michele
发明人： RADKE, William H. , VALI, Tommaso , INCARNATI, Michele
IPC分类号： G11C16/02 , G06F12/02 , G06F11/10
CPC分类号： G06F11/1048 , G06F3/0604 , G06F3/0608 , G06F3/0629 , G06F3/0631 , G06F3/064 , G06F3/0679 , G06F11/1068 , G06F11/1072 , G06F12/0207 , G06F12/0646 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C29/52
摘要： Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one block of memory cells. In another method, blocks are reconfigurable responsive to particular operating modes and/or desired levels of reliability of user data stored in a memory device.
摘要翻译：公开了存储器件和操作存储器件的方法。在一种这样的方法中，不同的存储器单元块具有用户数据空间和开销数据空间的不同配置。在至少一种方法中，开销数据分布在多于一个存储单元块内。在另一种方法中，响应于存储在存储器设备中的特定操作模式和/或用户数据的可靠性的期望级别来重新配置块。

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