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1. 发明申请

WO2013032928A1 THRESHOLD VOLTAGE COMPENSATION IN A MEMORY 审中-公开
标题翻译：存储器中的阈值电压补偿
公开(公告)号：WO2013032928A1
公开(公告)日：2013-03-07
申请号：PCT/US2012/052333
申请日：2012-08-24
申请人： MICRON TECHNOLOGY, INC. , MOSCHIANO, Violante , VALI, Tommaso , NASO, Giovanni , SARIN, Vishal , RADKE, William Henry , PEKNY, Theodore T.
发明人： MOSCHIANO, Violante , VALI, Tommaso , NASO, Giovanni , SARIN, Vishal , RADKE, William Henry , PEKNY, Theodore T.
IPC分类号： G11C16/34 , G11C16/26
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed "aggressor" memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

2. 发明申请

WO2011112354A3 SENSING OPERATIONS IN A MEMORY DEVICE 审中-公开
公开(公告)号：WO2011112354A3
公开(公告)日：2011-09-15
申请号：PCT/US2011/025799
申请日：2011-02-23
申请人： MICRON TECHNOLOGY, INC. , PABUSTAN, Jonathan , SARIN, Vishal , NGUYEN, Dzung
发明人： PABUSTAN, Jonathan , SARIN, Vishal , NGUYEN, Dzung
IPC分类号： G11C16/34 , G11C16/06 , G11C16/30
摘要： Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.

3. 发明申请

WO2009052273A1 MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT 审中-公开
标题翻译：内存设备程序窗口调整
公开(公告)号：WO2009052273A1
公开(公告)日：2009-04-23
申请号：PCT/US2008/080145
申请日：2008-10-16
申请人： MICRON TECHNOLOGY, INC. , SARIN, Vishal , ROOHPARVAR, Frankie, F. , PABUSTAN, Jonathan , HOEI, Jung-Sheng
发明人： SARIN, Vishal , ROOHPARVAR, Frankie, F. , PABUSTAN, Jonathan , HOEI, Jung-Sheng
IPC分类号： G11C16/10
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
摘要翻译：在一个或多个实施例中，公开了存储器件具有可编程窗口，其具有多个可编程级。移动编程窗口以补偿由于存储器件经历改变程序窗口的擦除/编程周期等因素而可实现的可靠程序和擦除阈值的变化。在初始擦除/编程周期之前确定初始编程窗口。然后随着编程窗口的改变，编程级别被移动，使得多个可编程级别仍然保留在程序窗口内并且随着程序窗口的改变而跟踪。

4. 发明申请

WO2009046171A1 REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE 审中-公开
标题翻译：减少程序干扰对存储器件的影响
公开(公告)号：WO2009046171A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/078546
申请日：2008-10-02
申请人： MICRON TECHNOLOGY, INC. , SARIN, Vishal
发明人： SARIN, Vishal
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C16/0483 , G11C16/10 , G11C16/3427
摘要： The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative voltage followed by a positive V pass voltage. The selected word lines are biased with a programming voltage. In one embodiment, the programming voltage is preceded by a negative voltage.
摘要翻译：半导体非易失性存储器件中的编程干扰效应通过利用负电压跟随正Vpass电压来偏置存储器块的未选字线来降低。所选择的字线被编程电压偏置。在一个实施例中，编程电压之前是负电压。

5. 发明申请

WO2008157141A1 PROGRAMMING A MEMORY WITH VARYING BITS PER CELL 审中-公开
标题翻译：编写具有每个细胞变化的位置的记忆
公开(公告)号：WO2008157141A1
公开(公告)日：2008-12-24
申请号：PCT/US2008/066465
申请日：2008-06-11
申请人： MICRON TECHNOLOGY, INC. , ROOHPARVAR, Frankie , SARIN, Vishal , HOEI, Jung, S.
发明人： ROOHPARVAR, Frankie , SARIN, Vishal , HOEI, Jung, S.
IPC分类号： G06F12/00
CPC分类号： G11C16/12 , G11C7/16 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C29/021 , G11C29/028 , G11C2211/5641
摘要： Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability.
摘要翻译：适于接收和发送表示两个或多个位的模拟数据信号的存储器件，例如有助于相对于传送指示各个位的数据信号的器件的数据传输速率的增加。控制器和读/写通道将数字位模式转换为模拟数据信号，以便以特定位容量级存储在存储器阵列中，以便实现期望的可靠性水平。

6. 发明申请

WO2008136911A1 EXPANDED PROGRAMMING WINDOW FOR NON-VOLATILE MULTILEVEL MEMORY CELLS 审中-公开
标题翻译：用于非易失性多层记忆体的扩展编程窗口
公开(公告)号：WO2008136911A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/004941
申请日：2008-04-16
申请人： MICRON TECHNOLOGY, INC. , SARIN, Vishal , HOEI, Jung, Sheng , ROOHPARVAR, Frankie, F.
发明人： SARIN, Vishal , HOEI, Jung, Sheng , ROOHPARVAR, Frankie, F.
IPC分类号： G11C11/56
CPC分类号： G11C11/5642 , G11C16/0483 , G11C2211/5621
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel memory cells. One method includes associating a different logical state with each of a number of different threshold voltage (Vt) distributions. In various embodiments, at least two Vt distributions include negative Vt levels. The method includes applying a read voltage to a word line of a selected cell while applying a pass voltage to word lines of unselected cells, applying a boost voltage to a source line coupled to the selected cell, applying a voltage greater than the boost voltage to a bit line of the selected cell, and sensing a current variation of the bit line in response to the selected cell changing from a non-conducting state to a conducting state.
摘要翻译：本公开的实施例提供了用于利用用于非易失性多层存储器单元的扩展编程窗口的方法，设备，模块和系统。一种方法包括将不同的逻辑状态与多个不同的阈值电压（Vt）分布中的每一个相关联。在各种实施例中，至少两个Vt分布包括负Vt电平。该方法包括将读取电压施加到所选择的单元的字线，同时向未选择的单元的字线施加通过电压，向耦合到所选择的单元的源极线施加升压电压，将大于升压电压的电压施加到所选择的单元的位线，并且响应于所选择的单元从非导通状态改变到导通状态来感测位线的当前变化。

7. 发明申请

WO2010059406A1 DATA TRANSFER AND PROGRAMMING IN A MEMORY DEVICE 审中-公开
标题翻译：数据传输和存储器件中的编程
公开(公告)号：WO2010059406A1
公开(公告)日：2010-05-27
申请号：PCT/US2009/062682
申请日：2009-10-30
申请人： MICRON TECHNOLOGY, INC. , SARIN, Vishal , ROOHPARVAR, Frankie, F.
发明人： SARIN, Vishal , ROOHPARVAR, Frankie, F.
IPC分类号： G11C16/34 , G11C16/10 , G11C16/26
CPC分类号： G11C7/1006 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C2211/5641
摘要： Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can readjust the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example.
摘要翻译：提供了用于存储器件，存储器件和存储器系统的数据传送和/或编程的方法。根据至少一种这样的方法，将附加数据附加到原始数据，并将所得数据编程在所选存储单元中。附加数据增加了原始数据的程序阈值电压余量。附加的数据可以是原始数据或逻辑零的副本。当读取所选择的存储单元时，存储器控制电路可以重新调整MSB字段中的原始数据，或者存储器控制电路可以读取整个编程数据并忽略LSB字段。

8. 发明申请

WO2010053593A1 CONFIGURABLE DIGITAL AND ANALOG INPUT/OUTPUT INTERFACE IN A MEMORY DEVICE 审中-公开
标题翻译：存储设备中的可配置数字和模拟输入/输出接口
公开(公告)号：WO2010053593A1
公开(公告)日：2010-05-14
申请号：PCT/US2009/041120
申请日：2009-04-20
申请人： MICRON TECHNOLOGY, INC. , ROOHPARVAR, Frankie, F. , SARIN, Vishal , HOEI, Jung-Sheng
发明人： ROOHPARVAR, Frankie, F. , SARIN, Vishal , HOEI, Jung-Sheng
IPC分类号： G11C7/10 , G11C16/10 , G11C16/26 , G11C7/16
CPC分类号： G11C11/5621 , G11C5/066 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/16
摘要： Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.
摘要翻译：公开了方法和存储器件，例如具有共享相同输入/输出焊盘的模拟路径和数字路径两者的存储器件。响应于指示信号的性质被传送到设备或从设备读取的命令信号来选择每个焊盘上的两个路径中的一个路径。每个数字路径包括用于锁存数字输入数据的锁存器。每个模拟路径包括采样/保持电路，用于存储被读取的模拟数据或被写入存储器件的模拟数据。

9. 发明申请

WO2009073162A2 SENSING MEMORY CELLS 审中-公开
标题翻译：传感记忆细胞
公开(公告)号：WO2009073162A2
公开(公告)日：2009-06-11
申请号：PCT/US2008/013255
申请日：2008-12-01
申请人： MICRON TECHNOLOGY, INC. , SARIN, Vishal , HOEI, Jung, Sheng , ROOHPARVAR, Frankie, F. , MAROTTA, Giulio-Giuseppe
发明人： SARIN, Vishal , HOEI, Jung, Sheng , ROOHPARVAR, Frankie, F. , MAROTTA, Giulio-Giuseppe
IPC分类号： G11C16/26 , G11C16/02 , G11C16/30
CPC分类号： G11C16/12 , G11C7/16 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5621 , G11C2211/5634 , G11C2211/5642
摘要： The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage (503) to a control gate of a memory cell (505) and to an analog- to-digital converter (ADC) (507). The aforementioned embodiment of a method also includes detecting an output of the ADC (515) at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry (511).
摘要翻译：本公开包括用于操作存储器单元的方法，设备，模块和系统。一种方法实施例包括将斜坡电压（503）施加到存储器单元（505）的控制栅极和模数转换器（ADC）（507）。上述方法的实施例还包括至少部分地响应于斜坡电压何时使存储器单元跳闸感测电路（511）来检测ADC（515）的输出。

10. 发明申请

WO2009051960A1 SENSING OF MEMORY CELLS IN NAND FLASH 审中-公开
标题翻译：在闪存中感应存储器
公开(公告)号：WO2009051960A1
公开(公告)日：2009-04-23
申请号：PCT/US2008/078397
申请日：2008-10-01
申请人： MICRON TECHNOLOGY, INC. , ROOHPARVAR, Frankie, F. , SARIN, Vishal
发明人： ROOHPARVAR, Frankie, F. , SARIN, Vishal
IPC分类号： G11C16/28
CPC分类号： G11C16/0483 , G11C16/26
摘要： An analog voltage NAND architecture non- volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing, hi a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash memory array is read by applying an elevated voltage to the source line, an elevated pass voltage (Vpass) is placed on the gates of the unselected cells of the string to place them in a pass through mode of operation, and a read gate voltage (Vg) is applied to the gate of the selected cell. The selected memory cell operates as a source follower to set a voltage on the coupled bit line at the read gate voltage minus the threshold voltage of the cell (Vg-Vt), allowing the voltage of the cell to be directly sensed or sampled.
摘要翻译：描述了模拟电压NAND架构非易失性存储器数据读取/验证过程和电路，其使用源跟随器电压感测来感测非易失性单元中的模拟电压。在源跟随器感测或读取操作中，单元的编程阈值电压 NAND结构闪存阵列的NAND串通过向源极线施加升高的电压而被读取，升高的通过电压（Vpass）被放置在串的未选择单元的栅极上，以将它们置于通过操作模式，并且读栅极电压（Vg）被施加到所选择的单元的栅极。所选择的存储单元作为源极跟随器工作，以在读取栅极电压减去单元的阈值电压（Vg-Vt）来设置耦合位线上的电压，从而允许单元的电压被直接感测或采样。

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