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1. 发明申请

WO2009093992A3 TRENCH MEMORY STRUCTURES AND OPERATION 审中-公开
公开(公告)号：WO2009093992A3
公开(公告)日：2009-07-30
申请号：PCT/US2007/085741
申请日：2007-11-28
申请人： MICRON TECHNOLOGY, INC. , GHODSI, Ramin
发明人： GHODSI, Ramin
IPC分类号： H01L21/28 , H01L21/336 , G11C16/04
摘要： Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non- volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over the trench, and, for certain embodiments, this control gate may extend into the trench. The charge carrier trapping sites may be discrete formations on a sidewall of a trench, a continuous layer extending from one sidewall to the other, or plugs extending between sidewalls.

2. 发明申请

WO2016064579A1 APPARATUSES AND METHODS FOR SEGMENTED SGS LINES 审中-公开
标题翻译： SEGMENTED SGS线的装置和方法
公开(公告)号：WO2016064579A1
公开(公告)日：2016-04-28
申请号：PCT/US2015/054412
申请日：2015-10-07
申请人： MICRON TECHNOLOGY, INC.
发明人： PAN, Feng , PARK, Jaekwan , GHODSI, Ramin
IPC分类号： G11C16/04 , G11C16/06 , G11C16/26
CPC分类号： G11C16/0483 , G11C8/12 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26
摘要： Apparatuses and methods for segmented SGS lines are described. An example apparatus may include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memory subblocks.
摘要翻译：描述了分段SGS线的装置和方法。示例性装置可以包括存储器块的第一和第二多个存储器子块。该装置可以包括与第一多个存储器子块相关联的第一选择栅极控制线和与第二多个存储器子块相关联的第二选择栅极控制线。第一选择栅极控制线可以耦合到第一多个存储器子块的第一多个选择栅极开关。第二选择栅极控制线可以耦合到第二多个存储器子块的第二多个选择栅极开关。第一和第二多个选择栅极开关可以耦合到源极。该装置可以包括与每个第一和第二多个存储器子块相关联的多个存储器访问线。

3. 发明申请

WO2008027409A2 NAND FLASH MEMORY PROGRAMMING 审中-公开
标题翻译： NAND闪存编程
公开(公告)号：WO2008027409A2
公开(公告)日：2008-03-06
申请号：PCT/US2007/018960
申请日：2007-08-28
申请人： MICRON TECHNOLOGY, INC. , GHODSI, Ramin , TANG, Qiang
发明人： GHODSI, Ramin , TANG, Qiang
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/12
摘要： A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described.
摘要翻译：一种对非易失性存储单元中的浮置栅极进行充电的方法包括：使存储单元内的衬底沟道达到第一电压，使控制栅极达到编程电压，并且在控制栅极处于编程电压的同时浮置衬底沟道电压。存储器件包括可操作以执行所述方法的状态机或控制器，并描述了这种状态机，存储器件和信息处理系统的操作。

4. 发明申请

WO2019045913A1 DETERMINING DATA STATES OF MEMORY CELLS 审中-公开
公开(公告)号：WO2019045913A1
公开(公告)日：2019-03-07
申请号：PCT/US2018/043624
申请日：2018-07-25
申请人： MICRON TECHNOLOGY, INC.
发明人： VALI, Tommaso , DE SANTIS, Luca , GHODSI, Ramin
IPC分类号： G11C16/10 , G11C16/26 , G11C16/34
摘要： Methods of operating a memory include determining a respective raw data value for each memory cell of a plurality of memory cells; determining the numbers of memory cells of a first subset of the plurality of memory cells having each raw data value as their respective raw data value; determining a respective raw data values representative of transition between each pair of adjacent data states responsive to the determined numbers of memory cells of the first subset of the plurality of memory cells for each raw data value; and determining a respective data state of the plurality of data states for each memory cell of a second subset of the plurality of memory cells responsive to its respective raw data value and to the determined raw data values representative of the transitions between adjacent data states.

5. 发明申请

WO2010147770A2 USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY 审中-公开
标题翻译：使用闪存存储器的非易失性存储器元件
公开(公告)号：WO2010147770A2
公开(公告)日：2010-12-23
申请号：PCT/US2010/037408
申请日：2010-06-04
申请人： MICRON TECHNOLOGY, INC. , GHODSI, Ramin
发明人： GHODSI, Ramin
IPC分类号： G11C11/00
CPC分类号： G11C16/0408 , G11C11/005 , G11C13/0002 , G11C16/10 , G11C16/26
摘要： Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.
摘要翻译：提供了操作存储器件的存储器件和方法，诸如涉及利用新兴非易失性存储器（NV）元件代替典型的静态和/或动态部件的存储器架构的存储器件和方法。新兴的NV存储器元件可以替代传统的锁存器，可以用作闪存阵列和外部设备之间的高速接口，并且还可以用作闪存阵列的高性能高速缓冲存储器。

6. 发明申请

WO2009061791A1 CONTROLLING A MEMORY DEVICE RESPONSIVE TO DEGRADATION 审中-公开
标题翻译：控制响应降解的存储器件
公开(公告)号：WO2009061791A1
公开(公告)日：2009-05-14
申请号：PCT/US2008/082445
申请日：2008-11-05
申请人： MICRON TECHNOLOGY, INC. , HA, Chang Wan , GHODSI, Ramin
发明人： HA, Chang Wan , GHODSI, Ramin
IPC分类号： G11C16/34 , G11C16/16 , G11C16/14
CPC分类号： G11C16/349
摘要： Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems capable of determining a degradation parameter associated with one or more memory cells. Disclosed devices and systems according to embodiments of the present invention include those that utilize the degradation parameter to adjust control signals coupled to the memory cells.
摘要翻译：本文公开的本发明的实施例包括诸如那些针对非易失性存储器件和能够确定与一个或多个存储器单元相关联的劣化参数的系统的器件，系统和方法。根据本发明的实施例的公开的设备和系统包括利用降级参数来调整耦合到存储器单元的控制信号的装置和系统。

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