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1. 发明申请

WO2014066462A4 APPARATUS AND METHOD FOR REFORMING RESISTIVE MEMORY CELLS 审中-公开
公开(公告)号：WO2014066462A4
公开(公告)日：2014-10-02
申请号：PCT/US2013066303
申请日：2013-10-23
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , WU ALBERT , LEE WINSTON , LEE PETER , CHANG RUNZI
发明人： SUTARDJA PANTAS , WU ALBERT , LEE WINSTON , LEE PETER , CHANG RUNZI
IPC分类号： G11C29/50 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C13/00 , G11C13/0033 , G11C13/004 , G11C29/50008 , G11C2013/0076 , G11C2013/0083
摘要： A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell.

2. 发明申请

WO2007109046A3 CROSS-POINT MEMORY ARRAY 审中-公开
标题翻译：交叉点记忆阵列
公开(公告)号：WO2007109046A3
公开(公告)日：2007-12-06
申请号：PCT/US2007006425
申请日：2007-03-14
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , WU ALBERT
发明人： SUTARDJA PANTAS , WU ALBERT
IPC分类号： H01L27/24 , G11C16/02
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141
摘要： A phase-change memory (PCM) system comprises a PCM cell array that comprises a plurality of PCM cells (8). Each of the PCM cells includes diode (13) arranged adjacent to a metallization layer (4); a heater element (16) arranged adjacent to the diode, and a phase-change material (15) arranged adjacent to the heater element.
摘要翻译：相变存储器（PCM）系统包括包含多个PCM单元（8）的PCM单元阵列。每个PCM单元包括邻近金属化层（4）布置的二极管（13）。与二极管相邻设置的加热器元件（16），以及邻近加热器元件设置的相变材料（15）。

3. 发明申请

WO2014066462A3 APPARATUS AND METHOD FOR REFORMING RESISTIVE MEMORY CELLS 审中-公开
标题翻译：用于重建抗性存储器细胞的装置和方法
公开(公告)号：WO2014066462A3
公开(公告)日：2014-07-03
申请号：PCT/US2013066303
申请日：2013-10-23
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , WU ALBERT , LEE WINSTON , LEE PETER , CHANG RUNZI
发明人： SUTARDJA PANTAS , WU ALBERT , LEE WINSTON , LEE PETER , CHANG RUNZI
IPC分类号： G11C29/50 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C13/00 , G11C13/0033 , G11C13/004 , G11C29/50008 , G11C2013/0076 , G11C2013/0083
摘要： A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell.
摘要翻译：存储器包括存储单元阵列，第一模块和第二模块。第一模块被配置为将存储器单元的第一状态与参考进行比较。存储器单元在存储器单元阵列中。第二模块被配置为在存储器单元的读取周期或写入周期之后并且基于该比较来重新构造存储器单元以调整存储器单元的第一状态和第二状态之间的差异。

4. 发明申请

WO2014062554A4 APPARATUS AND METHOD FOR REPAIRING RESISTIVE MEMORIES AND INCREASING OVERALL READ SENSITIVITY OF SENSE AMPLIFIERS 审中-公开
标题翻译：修复抗性记忆并提高感测放大器的整体读取灵敏度的装置和方法
公开(公告)号：WO2014062554A4
公开(公告)日：2014-06-12
申请号：PCT/US2013064801
申请日：2013-10-14
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , WU ALBERT , CHANG RUNZI , LEE WINSTON , LEE PETER
发明人： SUTARDJA PANTAS , WU ALBERT , CHANG RUNZI , LEE WINSTON , LEE PETER
IPC分类号： G11C29/02
CPC分类号： G11C7/065 , G11C7/06 , G11C7/067 , G11C7/1057 , G11C7/106 , G11C11/1653 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C29/026
摘要： A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch.
摘要翻译：存储器包括模块和解复用器。该模块配置为监测读出放大器的输出。读出放大器的每个输出被配置为处于第一状态或第二状态。该模块被配置为确定读出放大器的两个或更多个输出处于相同状态。相同的状态是第一状态或第二状态。该模块被配置为输出读出放大器的两个或更多个输出的状态。解复用器被配置为将读出放大器的两个或更多个输出的状态提供给锁存器。

5. 发明申请

WO2007109046B1 CROSS-POINT MEMORY ARRAY 审中-公开
标题翻译：交叉点记忆阵列
公开(公告)号：WO2007109046B1
公开(公告)日：2008-02-07
申请号：PCT/US2007006425
申请日：2007-03-14
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , WU ALBERT
发明人： SUTARDJA PANTAS , WU ALBERT
IPC分类号： H01L27/24 , G11C16/02
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141
摘要： A phase-change memory (PCM) system comprises a PCM cell array that comprises a plurality of PCM cells (8). Each of the PCM cells includes diode (13) arranged adjacent to a metallization layer (4); a heater element (16) arranged adjacent to the diode, and a phase-change material (15) arranged adjacent to the heater element.
摘要翻译：相变存储器（PCM）系统包括包含多个PCM单元（8）的PCM单元阵列。每个PCM单元包括邻近金属化层（4）布置的二极管（13）。与二极管相邻设置的加热器元件（16），以及邻近加热器元件设置的相变材料（15）。

6. 发明申请

WO2013078311A4 FREQUENCY SCALING OF VARIABLE SPEED SYSTEMS FOR FAST RESPONSE AND POWER REDUCTION 审中-公开
标题翻译：用于快速响应和降低功率的变速系统的频率标定
公开(公告)号：WO2013078311A4
公开(公告)日：2013-07-18
申请号：PCT/US2012066257
申请日：2012-11-21
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , SUTARDJA SEHAT
发明人： SUTARDJA PANTAS , SUTARDJA SEHAT
IPC分类号： G06F1/08 , G06F1/32 , H03L7/00
CPC分类号： H03K3/02 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.
摘要翻译：一种包括被配置为生成具有频率的时钟信号的多个放大器的系统。时钟信号被输入到处理器。放大器串联连接。最后一个放大器的输出被反馈到第一个放大器的输入端。每个放大器都有一个跨导。频率调整模块被配置为基于处理器的活动水平通过调整放大器的跨导来调整时钟信号的频率。

7. 发明申请

WO2011060248A4 CLOCK TURN-ON STRATEGY FOR POWER MANAGEMENT 审中-公开
标题翻译：电源管理的时钟开启策略
公开(公告)号：WO2011060248A4
公开(公告)日：2011-10-27
申请号：PCT/US2010056509
申请日：2010-11-12
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS
发明人： SUTARDJA PANTAS
IPC分类号： G06F1/30 , G06F1/08
CPC分类号： G06F21/50 , G06F1/08 , G06F1/305
摘要： A system includes a voltage sensing module and a frequency adjustment module. The voltage sensing module is configured to sense a supply voltage of a circuit block, generate a first control signal when the supply voltage is less than or equal to a first voltage, and generate a second control signal when the supply voltage is within a predetermined range of a second voltage. The frequency adjustment module is configured to set a frequency of a clock signal supplied to the circuit block to less than a normal operating frequency of the circuit block when the supply voltage is initially supplied to the circuit block after a power on reset operation and the first control signal or the second control signal is received.
摘要翻译：一种系统包括电压感测模块和频率调整模块。电压感测模块被配置为感测电路块的电源电压，当电源电压小于或等于第一电压时产生第一控制信号，并且当电源电压在预定范围内时产生第二控制信号的第二电压。频率调节模块被配置为：当在电源接通复位操作之后将电源电压初始提供给电路块时，将提供给电路块的时钟信号的频率设置为小于电路块的正常工作频率，并且第一控制信号或第二控制信号被接收。

8. 发明申请

WO2008073421A3 HYBRID NON-VOLATILE SOLID STATE MEMORY SYSTEM 审中-公开
公开(公告)号：WO2008073421A3
公开(公告)日：2008-07-31
申请号：PCT/US2007025312
申请日：2007-12-11
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS
发明人： SUTARDJA PANTAS
IPC分类号： G06F12/12 , G11C16/34
CPC分类号： G11C16/349 , G06F3/0616 , G06F3/0644 , G06F3/0679 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/3495 , G11C2211/5641
摘要： A solid state memory system comprises a first nonvolatile semiconductor (NVS) memory that has a first write cycle lifetime, a second nonvolatile semiconductor (NVS) memory that has a second write cycle lifetime that is different than the first write cycle lifetime, and a wear leveling module. The wear leveling module generates first and second wear levels for the first and second NVS memories based on the first and second write cycle lifetimes and maps logical addresses to physical addresses of one of the first and second NVS memories based on the first and second wear levels.

9. 发明申请

WO2007084751A3 FLASH MEMORY WITH CODING AND SIGNAL PROCESSING 审中-公开
标题翻译：具有编码和信号处理的闪存
公开(公告)号：WO2007084751A3
公开(公告)日：2008-01-10
申请号：PCT/US2007001623
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD , WU ZINING , SUTARDJA PANTAS
发明人： WU ZINING , SUTARDJA PANTAS
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1072 , G06F11/1068 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C29/00 , G11C2029/0411 , G11C2211/5641
摘要： A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.
摘要翻译：固态非易失性存储器单元部分地包括编码器，适用于存储由编码器编码的数据的多级固态非易失性存储器阵列，以及适于对从存储器阵列检索的数据进行解码的解码器。存储器阵列可以是闪存EEPROM阵列。存储器单元可选地包括调制器和解调器。由调制器调制的数据被存储在存储器阵列中。解调器解调从存储器阵列检索的调制数据。

10. 发明申请

WO2008013695A4 FILE SERVER FOR REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) SYSTEM 审中-公开
标题翻译：文件服务器用于冗余阵列的独立磁盘（RAID）系统
公开(公告)号：WO2008013695A4
公开(公告)日：2009-07-30
申请号：PCT/US2007016159
申请日：2007-07-17
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS
发明人： SUTARDJA PANTAS
IPC分类号： G06F11/10
CPC分类号： G06F3/0643 , G06F3/0604 , G06F3/067 , G06F11/08 , G06F11/1076 , G06F2211/109
摘要： A redundant array of independent disks (RAID) system comprises N storage arrays. Each of the N storage arrays comprise a target processing module and 1 to M hard disk drives, where M and N are integers greater than 1. A data processing module assigns a first data storage request for a first data block to one of the target processing modules for processing of error checking and correcting (ECC) data for the first data block. The one of the target processing modules sends a first portion of the first data block and ECC data associated with the first data block to another of the target processing modules.
摘要翻译：独立磁盘冗余阵列（RAID）系统包含N个存储阵列。 N个存储阵列中的每一个包括目标处理模块和1到M个硬盘驱动器，其中M和N是大于1的整数。数据处理模块将针对第一数据块的第一数据存储请求分配给目标处理中的一个用于处理第一数据块的错误检查和纠正（ECC）数据的模块。目标处理模块中的一个将第一数据块的第一部分和与第一数据块相关联的ECC数据发送给另一个目标处理模块。

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