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1. 发明申请

WO2007034384A2 SINGLE THRESHOLD AND SINGLE CONDUCTIVITY TYPE LOGIC 审中-公开
标题翻译：单路和单电导型逻辑
公开(公告)号：WO2007034384A2
公开(公告)日：2007-03-29
申请号：PCT/IB2006053281
申请日：2006-09-14
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN ACHT VICTOR M G , LAMBERT NICOLAAS , MIJIRITSKII ANDREI , WOERLEE PIERRE H
发明人： VAN ACHT VICTOR M G , LAMBERT NICOLAAS , MIJIRITSKII ANDREI , WOERLEE PIERRE H
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current pathes being coupled to a common note that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主要的电流裸片耦合到形成逻辑组件（400）的输出的公共音符。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

2. 发明申请

WO2009063400A3 ORIENTATION MEASUREMENT OF AN OBJECT 审中-公开
标题翻译：对象的方位测量
公开(公告)号：WO2009063400A3
公开(公告)日：2009-07-09
申请号：PCT/IB2008054719
申请日：2008-11-11
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN ACHT VICTOR M G , LAMBERT NICOLAAS
发明人： VAN ACHT VICTOR M G , LAMBERT NICOLAAS
IPC分类号： G01C21/16 , G01C25/00
CPC分类号： G01C21/165 , G01C25/005
摘要： There is provided an object orientation measurement system for improving the accuracy of a first estimate of the orientation of an object to which the system is attached, the system comprising an accelero meter for measuring a first acceleration of the object; and an estimation unit for providing a position or velocity of the object; processing means for comparing the first acceleration and output of the estimation unit to form a correction signal, and for applying the correction signal to the first estimate of the orientation of the object to produce a second estimate of the orientation of the object.
摘要翻译：提供了一种用于提高系统所附接的物体的取向的第一估计的准确度的物体定向测量系统，该系统包括用于测量物体的第一加速度的加速度计; 以及估计单元，用于提供所述物体的位置或速度; 处理装置，用于比较估计单元的第一加速度和输出以形成校正信号，并且用于将校正信号应用于对象的取向的第一估计，以产生对象的取向的第二估计。

3. 发明申请

WO2009031064A3 EXTRACTING INERTIAL AND GRAVITATIONAL VECTOR COMPONENTS FROM ACCELERATION MEASUREMENTS 审中-公开
标题翻译：提取加速度测量的惯性和粗略矢量分量
公开(公告)号：WO2009031064A3
公开(公告)日：2009-07-02
申请号：PCT/IB2008053399
申请日：2008-08-25
申请人： KONINKL PHILIPS ELECTRONICS NV , YIN BIN , VAN ACHT VICTOR M G , LAMBERT NICOLAAS
发明人： YIN BIN , VAN ACHT VICTOR M G , LAMBERT NICOLAAS
IPC分类号： A61B6/00 , A61B5/11 , G01C21/16 , G01P15/18
CPC分类号： A61B5/1126 , A61B5/1118 , A61B5/1122 , A61B2562/0219 , G01C21/16
摘要： This invention discloses method of extracting inertial Vi and gravitational Vg acceleration vector components from acceleration vector Va = Vi + Vg measured by an accelerometer when the absolute orientation of the accelerometer coordinate system relative to the earth coordinate system varies over time. A sequence of acceleration readout vectors Va [k] from the accelerometer is received. For a given sampling moment k a temporal estimate (I)g [k] is determined for the gravitational acceleration vector Vg, the temporal estimate being determined in the accelerometer coordinate system using the acceleration readout vectors from the accelerometer. A first estimate for the inertial acceleration vector (II)i [k] is set to zero. A measure of the difference between the readout vector Va [k] and the sum of (I)g [k] + (II)i [k] is determined and a measure of the difference in length between the estimate (II)g [k] and the actual gravitational acceleration vector Vg is determined. If the determined measures do not equal substantially to zero the estimates (II)g [k] and (II)i [k] are replaced by a next improved estimate and above mentioned steps are repeated.
摘要翻译：本发明公开了当加速度计坐标系相对于地球坐标系的绝对取向随时间变化时，由加速度计测量的加速度矢量Va = Vi + Vg提取惯性Vi和重力Vg加速度矢量分量的方法。接收来自加速度计的一系列加速度读出矢量Va [k]。对于给定的采样时刻k，对于重力加速度矢量V g确定时间估计（I）g [k]，使用来自加速度计的加速度读数矢量在加速度计坐标系中确定时间估计。惯性加速度矢量（II）i [k]的第一估计被设置为零。确定读出矢量Va [k]与（I）g [k] +（II）i [k]的和之间的差的度量，并且测量估计（II）g [ k]并且确定实际的重力加速度矢量Vg。如果确定的措施不等于零，则估计（II）g [k]和（II）i [k]被替换为下一个改进的估计，并且重复上述步骤。

4. 发明申请

WO2009077976A2 ORIENTATION MEASUREMENT OF AN OBJECT 审中-公开
标题翻译：对象的方位测量
公开(公告)号：WO2009077976A2
公开(公告)日：2009-06-25
申请号：PCT/IB2008055319
申请日：2008-12-16
申请人： KONINKL PHILIPS ELECTRONICS NV , PHILIPS INTELLECTUAL PROPERTY , VAN ACHT VICTOR M G , LAMBERT NICOLAAS , BONGERS EDWIN G J M , LANFERMANN GERD
发明人： VAN ACHT VICTOR M G , LAMBERT NICOLAAS , BONGERS EDWIN G J M , LANFERMANN GERD
IPC分类号： G01C17/28 , G01C21/16
CPC分类号： G01C17/28 , G01C21/165
摘要： There is provided an object orientation measurement system for calculating an estimate of the orientation of an object to which the system can be attached, the system comprising measurement means for taking measurements of a plurality of parametersused in calculating an estimate of the orientation of the object; and processing means for comparing a measurement of at least one of the parameters with a first predetermined value; and calculating an estimate of the orientation of the object using the measurements of the plurality of parameters, wherein the weighting of the measurement of the at least one parameter is adjusted relative to the measurement of at least one other parameter based on the result ofthe comparison.
摘要翻译：提供了一种用于计算系统可以附着到的物体的取向的估计的物体取向测量系统，该系统包括用于在计算物体的取向的估计中使用的多个参数的测量的测量装置; 以及处理装置，用于将至少一个参数的测量值与第一预定值进行比较; 以及使用所述多个参数的测量结果来计算所述对象的取向的估计，其中，基于所述比较的结果，相对于所述至少一个其他参数的所述测量来调整所述至少一个参数的所述测量的所述加权。

5. 发明申请

WO2008020389A3 FLASH MEMORY ACCESS CIRCUIT 审中-公开
标题翻译：闪存访问电路
公开(公告)号：WO2008020389A3
公开(公告)日：2008-10-16
申请号：PCT/IB2007053201
申请日：2007-08-13
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN ACHT VICTOR M G , LAMBERT NICOLAAS
发明人： VAN ACHT VICTOR M G , LAMBERT NICOLAAS
IPC分类号： G06F9/44 , G06F9/48
CPC分类号： G06F9/4812
摘要： A system comprises an instruction processor (10), a flash memory device (14a), a flash control circuit (14) and a working memory (16). Instructions of an interrupt program are kept stored in the flash memory device (14a). When the instruction processor (10) receives an interrupt signal, the instruction processor (10) executes loading instructions, to cause the flash control circuit (14) to load said instructions of the interrupt program from the flash memory device (14a) into the working memory (16). The instructions of the interrupt program are subsequently executed with the instruction processor (10) from the working memory (16). Preferably it is tested whether a copy of said instructions of the interrupt program is stored in the working memory (16) at the time of the interrupt. If the copy is found stored, execution of said instructions from the copy is started before completing execution of of access instructions that were in progress at the time of the interrupt. If the copy is not found stored, execution of the access instructions is first completed and subsequently the instruction processor (10) executes the loading instructions, followed by execution of the instructions of the copy of interrupt program from the working memory (16).
摘要翻译：一种系统包括指令处理器（10），闪存设备（14a），闪存控制电路（14）和工作存储器（16）。中断程序的指令保存在闪存设备（14a）中。当指令处理器（10）接收到中断信号时，指令处理器（10）执行加载指令，使得闪存控制电路（14）将来自闪存器件（14a）的中断程序的所述指令加载到工作中存储器（16）。中断程序的指令随后由指令处理器（10）从工作存储器（16）中执行。优选地，测试在中断时是否将中断程序的所述指令的副本存储在工作存储器（16）中。如果发现拷贝被存储，则在完成中断时正在进行的访问指令的执行之前，从拷贝开始执行所述指令。如果没有找到该副本，则首先完成访问指令的执行，随后指令处理器（10）执行装入指令，随后从工作存储器（16）执行中断程序副本的指令。

6. 发明申请

WO2005124787A2 ELECTRICAL DEVICE AND METHOD OF MANUFACTURING THEREFOR 审中-公开
标题翻译：电气设备及其制造方法
公开(公告)号：WO2005124787A2
公开(公告)日：2005-12-29
申请号：PCT/IB2005051893
申请日：2005-06-09
申请人： KONINKL PHILIPS ELECTRONICS NV , WOERLEE PIERRE H , WIDDERSHOVEN FRANCISCUS P , VAN ACHT VICTOR M G , IKKINK TEUNIS J , LAMBERT NICOLAAS , MARSMAN ALBERT W
发明人： WOERLEE PIERRE H , WIDDERSHOVEN FRANCISCUS P , VAN ACHT VICTOR M G , IKKINK TEUNIS J , LAMBERT NICOLAAS , MARSMAN ALBERT W
IPC分类号： G11C16/02 , H01L27/24
CPC分类号： G11C13/0011 , B82Y10/00 , G11C13/0004 , G11C13/0014 , H01L27/2409 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： The present invention relates to an electrical device (Fig. 6) having a programmable resistor (PR) connected in series to a punch-through diode (S). The invention also relates to a method of manufacturing such an electrical device. The method comprises the steps of: providing a stack comprising a first layer of a semiconductor material of a first conductivity type arranged between a second layer and a third layer of a semiconductor material of a second conductivity type opposite to the first conductivity type, and providing a layer of material having a programmable resistivity, the layer of material having the programmable resistivity being in electrical contact with one of the second and third layer of the semiconductor material.
摘要翻译：本发明涉及具有与穿通二极管（S）串联连接的可编程电阻器（PR）的电气设备（图6）。本发明还涉及一种制造这种电气装置的方法。该方法包括以下步骤：提供堆叠，其包括第一导电类型的第一层和第三导电类型的第二层与第一导电类型相反的第二导电类型的第三层和第三层之间，具有可编程电阻率的材料层，具有可编程电阻率的材料层与半导体材料的第二和第三层之一电接触。

7. 发明申请

WO2007096844A3 MEMORY WITH BLOCK-ERASABLE LOCATIONS 审中-公开
标题翻译：具有可擦除位置的记忆
公开(公告)号：WO2007096844A3
公开(公告)日：2008-01-03
申请号：PCT/IB2007050605
申请日：2007-02-26
申请人： NXP BV , VAN ACHT VICTOR M G , LAMBERT NICOLAAS
发明人： VAN ACHT VICTOR M G , LAMBERT NICOLAAS
IPC分类号： G06F12/02
CPC分类号： G06F12/0246
摘要： A non-volatile main memory (10) comprises a plurality of physical blocks of memory locations. Pointing information (112a-c, 114a-c) is stored in the main memory (10), the pointing information comprising pointers (112a-c) to used blocks in use for particular functions and pointers (114a-c) to free blocks that are free for future use for the particular functions. The free blocks to replace selected ones of the used blocks. After this happens an updated version of the pointing information may be written to the main memory only after using at least two of the free blocks as replacements. On start up at least one of the pointers (114a-c) to the free blocks is used to access at least one of the free blocks and to determining whether the accessed free block has been used as a replacement for a particular one of the used blocks. If so, the free block is used instead of the particular one of the used blocks.
摘要翻译：非易失性主存储器（10）包括存储器位置的多个物理块。指向信息（112a-c，114a-c）被存储在主存储器（10）中，指向信息包括用于特定功能的使用块和指针（114a-c）的指针（112a-c）可供日后使用，用于特定功能。可用块来替换所使用的块中选定的块。发生这种情况之后，只有在使用至少两个空闲块作为替换之后，可以将更新版本的指向信息写入主存储器。在启动时，使用至空闲块的至少一个指针（114a-c）来访问至少一个空闲块并且确定所访问的空闲块是否已被用作替代所使用的特定一个块。如果是这样，则使用空闲块代替所使用的块中的特定块。

8. 发明申请

WO2007066276A3 AN ELECTRONIC CIRCUIT WITH A MEMORY MATRIX 审中-公开
标题翻译：具有存储矩阵的电子电路
公开(公告)号：WO2007066276A3
公开(公告)日：2007-10-11
申请号：PCT/IB2006054583
申请日：2006-12-04
申请人： NXP BV , LAMBERT NICOLAAS , VAN ACHT VICTOR M G , WOERLEE PIERRE H , MIJIRITSKII ANDREI
发明人： LAMBERT NICOLAAS , VAN ACHT VICTOR M G , WOERLEE PIERRE H , MIJIRITSKII ANDREI
IPC分类号： G11C16/02 , H01L27/105
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.
摘要翻译：电子电路包括具有存储单元（16）的行和列的存储矩阵（60）。为每行设置第一行导体（10,12）。提供第二行导体（12）用于连续重叠相邻行对。为每个列提供列导体（14）。每个存储单元（16）包括存取晶体管（160），节点（166）和第一和第二电阻性存储元件（162,164）。存取晶体管（160）优选地是垂直晶体管，其具有耦合到存储单元（16）的行的第一行导体（10）的控制电极，耦合在用于列的列导体（14）之间的主电流通道的存储单元（160）和节点（166）。第一和第二电阻性存储器元件（162,164）耦合在用于存储器单元所属的行对的节点（166）和第二行导体（12）之间。

9. 发明申请

WO2007102117A3 ELECTRONIC CIRCUIT WITH A MEMORY MATRIX THAT STORES PAGES INCLUDING EXTRA DATA 审中-公开
标题翻译：具有包含额外数据的存储器的存储器矩阵的电子电路
公开(公告)号：WO2007102117A3
公开(公告)日：2007-11-15
申请号：PCT/IB2007050719
申请日：2007-03-05
申请人： NXP BV , VAN ACHT VICTOR M G , LAMBERT NICOLAAS
发明人： VAN ACHT VICTOR M G , LAMBERT NICOLAAS
IPC分类号： G06F11/10
CPC分类号： G06F11/1068
摘要： An apparatus comprises a memory with a matrix (10) with rows and columns of memory cells. A read access circuit (14, 16, 18) executes a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix (10) and to output data from the retrieval unit. A processing circuit (12) coupled to the read access circuit (14, 16, 18) is configured to execute an extra read operation involving issuing the read command, receiving the extra data (24), performing error detection on only the extra data (24), using an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data (24) using data from the retrieval unit including the payload data (22), according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data (24). The processing circuit (12) performs further processing using the data from the extra data (22) or the corrected extra data, dependent on whether the error detection indicates an error in the extra data (22).
摘要翻译：一种装置包括具有带有存储单元的行和列的矩阵（10）的存储器。读取访问电路（14,16,18）执行读取命令以从矩阵（10）读取包括来自存储器单元的行的数据的检索单元，并从检索单元输出数据。耦合到读取访问电路（14,16,18）的处理电路（12）被配置为执行涉及发出读取命令的额外读取操作，接收附加数据（24），仅对附加数据执行错误检测 24），使用其中对所述额外数据进行编码的错误检测码，根据来自所述有效载荷数据（22）的检索单元的数据，使用来自所述附加数据（24）的数据对所述数据进行有条件地执行错误校正，所述纠错码其中检索单元被编码，如果错误检测指示额外数据（24）中的错误。处理电路（12）根据来自额外数据（22）的数据或校正的附加数据，根据该错误检测是否指示额外数据（22）中的错误，进行进一步处理。

10. 发明申请

WO2004042557A3 STORING BIOS IN PERSISTENT SYSTEM MEMORY 审中-公开
标题翻译：存储系统内存中的BIOS
公开(公告)号：WO2004042557A3
公开(公告)日：2004-11-04
申请号：PCT/IB0304456
申请日：2003-10-08
申请人： KONINKL PHILIPS ELECTRONICS NV , FONTIJN WILHELMUS F J , LAMBERT NICOLAAS , JOCHEMSEN ROBERT , DENISSEN ADRIANUS J M
发明人： FONTIJN WILHELMUS F J , LAMBERT NICOLAAS , JOCHEMSEN ROBERT , DENISSEN ADRIANUS J M
IPC分类号： G06F9/00 , G06F9/445
CPC分类号： G06F9/4401
摘要： When booting a personal computer, it needs to find instructions immediately to tell it what to run to start up the personal computer. These it finds within the so-called basic input/output system (BIOS) program. Usually the BIOS program is stored in a separate location, for example a ROM. It is usually shadowed into system memory (SM) to speed up its operation. The copying of the BIOS program to system memory (SM), amongst others, causes the boot process to be a relatively slow process. In the present invention, the system memory (SM) comprises a persistent system memory (PSM) and the BIOS program is stored in the persistent system memory (PSM). Furthermore, selected information used by the BIOS program is stored in persistent system memory (PSM) as well. As a result, the speed of booting the personal computer is significantly increased.

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