专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2006026055A3 MOS VARACTOR USING ISOLATION WELL 审中-公开
公开(公告)号：WO2006026055A3
公开(公告)日：2006-03-09
申请号：PCT/US2005/027738
申请日：2005-08-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COOLBAUGH, Douglas, D. , HERSHBERGER, Douglas, B. , RASSEL, Robert, M.
发明人： COOLBAUGH, Douglas, D. , HERSHBERGER, Douglas, B. , RASSEL, Robert, M.
IPC分类号： H01L27/08 , H01L29/93
摘要： The present invention provides a varactor (22) that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor (22). The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate (12) of a first conductivity type and optionally a subcollector (14) or isolation well (i.e., doped region) of a second conductivity type located below an upper region (11) of the substrate (12), the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions (16) are formed in the upper region (11) of the substrate (12) and then a well region is formed in the upper region (11) of the substrate (12). In some cases, the doped region (14) is formed at this point of the inventive process. The well region includes outer well regions (20A and 20C) of the second conductivity type and an inner well region (20B) of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region (16). A field effect transistor having at least a gate conductor (26) of the first conductivity type is then formed above the inner well region (20B).

2. 发明申请

WO2010056502A1 SILICIDED TRENCH CONTACT TO BURIED CONDUCTIVE LAYER 审中-公开
标题翻译：硅胶触点接触导电层
公开(公告)号：WO2010056502A1
公开(公告)日：2010-05-20
申请号：PCT/US2009/062139
申请日：2009-10-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COOLBAUGH, Douglas, D. , JOHNSON, Jeffrey, B. , LINDGREN, Peter, J. , LIU, Xuefeng , NAKOS, James, S. , ORNER, Bradley, A. , RASSEL, Robert, M. , SHERIDAN, David, C.
发明人： COOLBAUGH, Douglas, D. , JOHNSON, Jeffrey, B. , LINDGREN, Peter, J. , LIU, Xuefeng , NAKOS, James, S. , ORNER, Bradley, A. , RASSEL, Robert, M. , SHERIDAN, David, C.
IPC分类号： H01L21/768
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/823475 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L21/8249
摘要： A trench contact suicide (78) is formed on an inner wall of a contact trench (63) that reaches to a buried conductive layer (30) in a semiconductor substrate (8) to reduce parasitic resistance of a reach through structure. The trench contact suicide (78) is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate (8). The trench (63) is subsequently filled with a middle-of-line (MOL) dielectric (92). A contact via (98) may be formed on the trench contact suicide (78). The trench contact suicide (78) may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物（78）形成在接触沟槽（63）的内壁上，该接触沟槽（63）到达半导体衬底（8）中的掩埋导电层（30），以减小到达结构的寄生电阻。沟槽接触硅化物（78）形成在沟槽的底部，沟槽的侧壁上，半导体衬底（8）的顶表面的一部分上。沟槽（63）随后用中间线（MOL）电介质（92）填充。接触通孔（98）可以形成在沟槽接触硅化物（78）上。沟槽接触硅化物（78）可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应而形成。

3. 发明申请

WO2006073943A3 METHOD FOR FORMING A ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT 审中-公开
公开(公告)号：WO2006073943A3
公开(公告)日：2006-07-13
申请号：PCT/US2005/047085
申请日：2005-12-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COOLBAUGH, Douglas, D. , FURKAY, Stephen, S. , JOHNSON, Jeffrey, B. , RASSEL, Robert, M.
发明人： COOLBAUGH, Douglas, D. , FURKAY, Stephen, S. , JOHNSON, Jeffrey, B. , RASSEL, Robert, M.
IPC分类号： H01L21/20 , H01L29/93
摘要： A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.

4. 发明申请

WO2006017600A2 FEOL/MEOL METAL RESISTOR FOR HIGH END CMOS 审中-公开
标题翻译：用于高端CMOS的FEOL / MEOL金属电阻
公开(公告)号：WO2006017600A2
公开(公告)日：2006-02-16
申请号：PCT/US2005/027618
申请日：2005-08-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHINTHAKINDI, Anil, K. , COOLBAUGH, Douglas, D. , RAMACHANDRAN, Vidhya , RASSEL, Robert, M.
发明人： CHINTHAKINDI, Anil, K. , COOLBAUGH, Douglas, D. , RAMACHANDRAN, Vidhya , RASSEL, Robert, M.
IPC分类号： H01L29/76 , H01L29/00
CPC分类号： H01L28/24 , H01L27/0629 , H01L29/7833
摘要： A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure (32) into a CMOS technology are provided.
摘要翻译：一种FEOL / MEOL金属电阻器（32），其具有紧密的薄层电阻容差（约5％或更小），高电流密度（约0.5mA /微米或更大的量级），比标准BEOL金属电阻器更低的寄生效应比扩散电阻器和更低的TCR，以及将这种金属电阻器结构（32）集成到CMOS技术中的各种方法。

5. 发明申请

WO2005034202A2 PRECISION POLYSILICON RESISTOR PROCESS 审中-公开
标题翻译：精密多晶硅电阻器工艺
公开(公告)号：WO2005034202A2
公开(公告)日：2005-04-14
申请号：PCT/US2004/032406
申请日：2004-09-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COOLBAUGH, Douglas, D. , GREER, Heidi, L. , RASSEL, Robert, M.
发明人： COOLBAUGH, Douglas, D. , GREER, Heidi, L. , RASSEL, Robert, M.
IPC分类号： H01L
CPC分类号： H01L27/0738 , H01L27/0802 , H01L28/20
摘要： A process is disclosed for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process generally includes performing an emitter / FET activation rapid thermal anneal (RTA) on a wafer having partially formed polysilicon resistors, followed by steps of depositing a protective dielectric layer (62) on the polysilicon, (56) implanting a dopant (64) through the protective dielectric layer into the polysilicon (56) to define the resistance of the polysilicon resistors, and forming a silicide (66).
摘要翻译：公开了一种制造精确的多晶硅电阻器的方法，其更精确地控制所制造的多晶硅电阻器的薄层电阻率的公差。该工艺通常包括在具有部分形成的多晶硅电阻器的晶片上执行发射极/ FET激活快速热退火（RTA），随后在多晶硅上沉积保护性电介质层（62），（56）注入掺杂剂（64）通过保护电介质层进入多晶硅（56）以限定多晶硅电阻器的电阻，并形成硅化物（66）。

6. 发明申请

WO2012106101A2 A SCHOTTKY BARRIER DIODE, A METHOD OF FORMING THE DIODE AND A DESIGN STRUCTURE FOR THE DIODE 审中-公开
标题翻译：肖特基势垒二极管，形成二极管的方法和二极管的设计结构
公开(公告)号：WO2012106101A2
公开(公告)日：2012-08-09
申请号：PCT/US2012/021483
申请日：2012-01-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , RASSEL, Robert, M. , STIDHAM, Mark, E.
发明人： RASSEL, Robert, M. , STIDHAM, Mark, E.
IPC分类号： H01L29/872 , H01L21/328
CPC分类号： H01L29/66143 , G06F17/5068 , H01L29/872
摘要： Disclosed are embodiments of a Schottky barrier diode (100). This Schottky barrier diode can be formed in a semiconductor substrate (101) having a doped region (110) with a first conductivity type. A trench isolation structure (120) can laterally surround a section (111) of the doped region at the top surface (102) of the substrate. A semiconductor layer (150) can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion (151) over the defined section (111) of the doped region and a guardring portion (152) over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer (140) can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.
摘要翻译：公开了肖特基势垒二极管（100）的实施例。该肖特基势垒二极管可以形成在具有第一导电类型的掺杂区域（110）的半导体衬底（101）中。沟槽隔离结构（120）可横向包围衬底的顶表面（102）处的掺杂区域的部分（111）。半导体层（150）可以位于衬底的顶表面上。该半导体层可以具有在掺杂区的限定部分（111）上方的肖特基势垒部分（151）和在肖特基势垒部分的侧向包围的沟槽隔离结构上的防护部分（152）。肖特基势垒部分可以具有第一导电类型，并且防护部分可以具有不同于第一导电类型的第二导电类型。金属硅化物层（140）可以覆盖半导体层。还公开了形成该肖特基势垒二极管的方法和用于肖特基势垒二极管的设计结构的实施例。

7. 发明申请

WO2009149221A1 INTERLEVEL CONDUCTIVE LIGHT SHIELD 审中-公开
标题翻译：交互式导光灯
公开(公告)号：WO2009149221A1
公开(公告)日：2009-12-10
申请号：PCT/US2009/046188
申请日：2009-06-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GAMBINO, Jeffrey, P. , HE, Zhong-xiang , OGG, Kevin, N. , RASSEL, Richard, J. , RASSEL, Robert, M.
发明人： GAMBINO, Jeffrey, P. , HE, Zhong-xiang , OGG, Kevin, N. , RASSEL, Richard, J. , RASSEL, Robert, M.
IPC分类号： G01J1/42
CPC分类号： H01L27/14623 , H01L27/1463 , H01L27/14632
摘要： A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure The conductive light shiel covers a floating drain of an image sensor pixel cell A second dielectric layer is formed over the conductive light shield and at least on via extending from a top surface of the second dielectnic layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.
摘要翻译：在金属互连结构中的通孔电平的第一电介质层上形成导电屏蔽。导电光罩覆盖图像传感器像素单元的浮动漏极。第二介电层形成在导电光屏蔽上，并且至少在通孔在金属互连结构中形成从第二介电层的顶表面延伸到第一电介质层的底表面。导电屏蔽可以形成在半导体衬底的顶表面和第一金属线之间的接触电平内或者可以通过两个金属线路电平之间的电平形成在任何金属互连中。由于通过导电光屏蔽而在浮动漏极上阻挡光，本发明的图像传感器像素单元不太容易产生噪声。

8. 发明申请

WO2012012157A2 SCHOTTKY BARRIER DIODE WITH PERIMETER CAPACITANCE WELL JUNCTION 审中-公开
标题翻译：肖特基二极管与周边电容良好连接
公开(公告)号：WO2012012157A2
公开(公告)日：2012-01-26
申请号：PCT/US2011/042296
申请日：2011-06-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Frederick, G. , LARY, Jenifer, E. , RASSEL, Robert, M. , STIDHAM, Mark, E.
发明人： ANDERSON, Frederick, G. , LARY, Jenifer, E. , RASSEL, Robert, M. , STIDHAM, Mark, E.
IPC分类号： H01L29/872 , H01L29/47
CPC分类号： H01L29/872 , H01L21/761 , H01L29/0619 , H01L29/0646 , H01L29/0692 , H01L29/66143
摘要： A Schottky barrier diode comprises a first-type substrate (100), a second-type well isolation region (102) on the first-type substrate, and a first-type well region (110) on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring (106) is on the second-type well isolation region. A second-type well region (104) is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region (108) is on the second-type well region, and a first-type contact region (112) contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer (124) is on the first- type contact region and a second ohmic metallic layer (126) is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode.
摘要翻译：肖特基势垒二极管包括第一类型衬底（100），第一类型衬底上的第二类型阱隔离区（102）和第二类型阱隔离区上的第一类型阱区（110）。在这里的实施例中，被称为周边电容阱接合环（106）的特征在第二类型的隔离区域上。第二类型井区域（104）位于第二类型井隔离区域上。周边电容阱接合环位于第一类型阱区域和第二类型阱区域之间并分离。第二类型接触区域（108）位于第二类型阱区域上，并且第一类型接触区域（112）接触第一类型阱区域的内部部分。第一类型阱区域的内部位于第一类型接触区域的中心内。另外，第一欧姆金属层（124）在第一类型接触区域上，第二欧姆金属层（126）位于第一类型阱区域上。第一欧姆金属层在构成肖特基势垒二极管的肖特基势垒的结处接触第二欧姆金属层。

9. 发明申请

WO2009003012A1 JUNCTION FIELD EFFECT TRANSISTOR WITH A HYPERABRUPT JUNCTION 审中-公开
标题翻译：具有高压接点的结型场效应晶体管
公开(公告)号：WO2009003012A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/068139
申请日：2008-06-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ESHUN, Ebenezer, E. , JOHNSON, Jeffrey, B. , PHELPS, Richard, A. , RASSEL, Robert, M. , ZIERAK, Michael, L.
发明人： ESHUN, Ebenezer, E. , JOHNSON, Jeffrey, B. , PHELPS, Richard, A. , RASSEL, Robert, M. , ZIERAK, Michael, L.
IPC分类号： H01L29/80 , H01L21/338 , H01L29/812
CPC分类号： H01L29/808 , H01L27/0617 , H01L27/098 , H01L29/36 , H01L29/66901
摘要： A junction field effect transistor (JFET) (Fig. 4) has a hyperabrupl junction laj cr (54) that functions as a channel of a JFFT. The hyperabrupt junction layer (54) is formed by two dopant profiles (50. 52) of opposite t}pes such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body ( 16) that is doped with the same type of dopants as the gate. This is in contrast with conventional JI7KTs that have a body that is doped with the opposite conductivity type as the gate. The body ( 16) may be electrically decoupled from (Figure 4, 10 and 30) the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate (Figure 8. 16 and 1 10). The capability to form a thin hyperabrupt junction layer (54) allows formation of a JFET in a semiconductor-on-insulator substrate (Figure 11. 210. 230).
摘要翻译：结型场效应晶体管（JFET）（图4）具有作为JFFT通道发挥功能的超级联结结点laj cr（54）。超破裂结层（54）由相对的t} pes的两个掺杂剂轮廓（50.52）形成，使得一个掺杂剂浓度分布在另一个掺杂剂分布的尾端处具有峰值浓度深度。通道的电压偏置由掺杂有与栅极相同类型的掺杂剂的体（16）提供。这与传统的JI7KT相反，传统的JI7KT具有以与栅极相反的导电类型掺杂的主体。主体（16）可以通过在主体和衬底之间形成的另一个反向偏置连接点或者在主体和衬底之间的掩埋导体层之间（图8,10和30）与衬底电气去耦合（图8,10和30）和110）。形成薄的超破坏结层（54）的能力允许在绝缘体上半导体衬底中形成JFET（图11,210,230）。

10. 发明申请

WO2007082200A2 SEMICONDUCTOR STRUCTURE INCLUDING TRENCH CAPACITOR AND TRENCH RESISTOR 审中-公开
标题翻译：半导体结构，包括TRENCH电容和TRENCH RESISTOR
公开(公告)号：WO2007082200A2
公开(公告)日：2007-07-19
申请号：PCT/US2007/060266
申请日：2007-01-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHENG, Kangguo , RASSEL, Robert, M.
发明人： CHENG, Kangguo , RASSEL, Robert, M.
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L27/016 , H01L27/0682 , H01L28/20 , H01L29/66181
摘要： A structure and a method for fabrication of the structure use a capacitor trench (CT) for a trench capacitor and a resistor trench (RT) for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench (CT) has a linewidth dimension (LWC) narrower than the resistor trench (RT). The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material (18a, 18b) at a periphery of the resistor trench (RT) and a resistor material (20) at a central portion of the resistor trench (RT).
摘要翻译：用于制造结构的结构和方法使用用于沟槽电容器的电容器沟槽（CT）和用于沟槽电阻器的电阻器沟槽（RT）。该结构通常是半导体结构。首先，电容器沟槽（CT）具有比电阻器沟槽（RT）窄的线宽尺寸（LWC）。沟槽线宽差提供了制造沟槽电容器和沟槽电阻器的有效方法。在第二种情况下，沟槽电阻器包括在电阻器沟槽（RT）的外围的导体材料（18a，18b）和电阻器沟槽（RT）的中心部分处的电阻材料（20）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式