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    • 2. 发明申请
    • MOS VARACTOR USING ISOLATION WELL
    • MOS变压器采用隔离井
    • WO2006026055A2
    • 2006-03-09
    • PCT/US2005027738
    • 2005-08-05
    • IBMCOOLBAUGH DOUGLAS DHERSHBERGER DOUGLAS BRASSEL ROBERT M
    • COOLBAUGH DOUGLAS DHERSHBERGER DOUGLAS BRASSEL ROBERT M
    • H01L29/94H01L21/20
    • H01L29/93H01L29/94
    • The present invention provides a varactor (22) that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor (22). The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate (12) of a first conductivity type and optionally a subcollector (14) or isolation well (i.e., doped region) of a second conductivity type located below an upper region (11) of the substrate (12), the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions (16) are formed in the upper region (11) of the substrate (12) and then a well region is formed in the upper region (11) of the substrate (12). In some cases, the doped region (14) is formed at this point of the inventive process. The well region includes outer well regions (20A and 20C) of the second conductivity type and an inner well region (20B) of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region (16). A field effect transistor having at least a gate conductor (26) of the first conductivity type is then formed above the inner well region (20B).
    • 本发明提供了具有增加的可调谐性和高品质因数Q的变容二极管(22)以及制造变容二极管(22)的方法。 本发明的方法可以集成到常规的CMOS处理方案中或者集成到传统的BiCMOS处理方案中。 该方法包括提供包括第一导电类型的半导体衬底(12)和可选地位于第二导电类型的上部区域(11)下方的第二导电类型的子集电极(14)或隔离阱(即,掺杂区域) 衬底(12),第一导电类型不同于所述第二导电类型。 接下来,在衬底(12)的上部区域(11)中形成多个隔离区域(16),然后在衬底(12)的上部区域(11)中形成阱区域。 在某些情况下,掺杂区(14)在本发明方法的这一点形成。 阱区包括第二导电类型的外阱区(20A和20C)和第一导电类型的内阱区(20B)。 所述阱区的每个阱在上表面处被隔离区(16)分隔开。 然后在内阱区(20B)上方形成至少具有第一导电类型的栅极导体(26)的场效应晶体管。