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    • 1. 发明申请
    • EMBEDDED ECC ADDRESS MAPPING
    • 嵌入式ECC地址映射
    • WO2014209936A1
    • 2014-12-31
    • PCT/US2014/043766
    • 2014-06-24
    • INTEL CORPORATIONVOGT, Pete D.
    • VOGT, Pete D.
    • G01F11/10G06F12/02
    • G06F11/1052
    • Apparatus, systems, and methods to embed ECC data with cacheline data in a memory page are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive a request to read or write data to a memory device, wherein the data is mapped to a memory page comprising a plurality of cache lines, displace at least a portion of the plurality of cache lines to embed error correction code information with the data, and remap the portion of the plurality of cache lines to another memory location, and retrieve or store the data and the error correction code information on the memory page. Other embodiments are also disclosed and claimed.
    • 描述了将ECC数据与高速缓存线数据嵌入存储器页面的装置,系统和方法。 在一个实施例中,电子设备包括处理器和存储器控制逻辑,用于接收将数据读取或写入存储器设备的请求,其中数据被映射到包括多个高速缓存行的存储器页面,将至少一部分 以将所述数据的纠错码信息嵌入到所述多个高速缓存行中,并且将所述多个高速缓存行的所述部分重新映射到另一个存储器位置,并且将所述数据和所述纠错码信息检索或存储在所述存储器页面上。 还公开并要求保护其他实施例。
    • 3. 发明申请
    • EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE
    • 扩展平台,每个CPU插槽有额外的内存模块插槽,配置提高性能
    • WO2018064424A1
    • 2018-04-05
    • PCT/US2017/054190
    • 2017-09-28
    • INTEL CORPORATION
    • QUERBACH, BruceVOGT, Pete D.
    • G11C5/04G06F1/18
    • Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive at least one memory module, the second row of elements positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.
    • 描述了包括配置为接受CPU和存储器模块的印刷电路板的电子设备和方法。 一种装置包括印刷电路板(PCB),该印刷电路板包括限定长度和宽度的印刷电路板,该长度大于宽度。 该装置包括PCB上的第一行元件,包括配置为接收至少一个存储器模块的第一存储器区域。 该装置包括在PCB上的第二行元件,包括被配置为容纳第一CPU的第一中央处理单元(CPU)插槽以及被配置为容纳第二CPU的第二CPU插槽,第一CPU插槽和第二CPU插槽 沿着PCB的宽度并排放置。 该装置还包括在PCB上的第三行元件,包括配置为接收至少一个存储器模块的第二存储器区域,第二行元件位于第一行元件和第三行元件之间。 描述并要求保护其他实施例。