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1. 发明申请

WO2018009171A1 RLINK - DIE TO DIE CHANNEL INTERCONNECT CONFIGURATIONS TO IMPROVE SIGNALING 审中-公开
标题翻译： RLINK - 模切通道互连配置以改善信号传输
公开(公告)号：WO2018009171A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040912
申请日：2016-07-02
申请人： INTEL CORPORATION , AYGUN, Kemal , DISCHLER, Richard J. , MORRISS, Jeff C. , QIAN, Zhiguo , GOMES, Wilfred , ZHANG, Yu Amos , VISWANATH, Ram S. , SWAMINATHAN, Rajasekaran Raja , SRINIVASAN, Sriram , MEKONNEN, Yidnekachew S. , GANESAN, Sanka Gans , ROYTMAN, Eduard , MANUSHAROW, Mathew J.
发明人： AYGUN, Kemal , DISCHLER, Richard J. , MORRISS, Jeff C. , QIAN, Zhiguo , GOMES, Wilfred , ZHANG, Yu Amos , VISWANATH, Ram S. , SWAMINATHAN, Rajasekaran Raja , SRINIVASAN, Sriram , MEKONNEN, Yidnekachew S. , GANESAN, Sanka Gans , ROYTMAN, Eduard , MANUSHAROW, Mathew J.
IPC分类号： H01L25/065 , H01L23/60 , H01L23/498 , H01L23/525 , H01L23/00
摘要： Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
摘要翻译：集成电路（IC）芯片裸片至裸片通道互连配置（用于其制造的系统及方法）可通过包括裸片上导入结构来改善进入并通过单端总线数据信号通信通道的信号传输; 片上互连功能; 封装内第一级裸片凸点设计和地面织带结构; 封装式高速水平数据信号传输线; 封装上垂直数据信号传输互连; 和/或封装内电光（EO）连接器，用于改进信号连接和通过延伸穿过一个或多个半导体器件封装器件的数据信号通道的传输，所述半导体器件封装器件可包括电光（EO））连接器，在该连接器上可以安装至少一个封装器件，和/或作为半导体器件封装在封装式封装配置中。

2. 发明申请

WO2018182598A1 SIDE MOUNTED INTERCONNECT BRIDGES 审中-公开
公开(公告)号：WO2018182598A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/024803
申请日：2017-03-29
申请人： INTEL CORPORATION , HOSSAIN, MD Altaf , DORAN, Kevin, J. , ZHANG, Yu Amos , QIAN, Zhiguo
发明人： HOSSAIN, MD Altaf , ZHANG, Yu Amos , QIAN, Zhiguo
IPC分类号： H01L25/18 , H01L25/16 , H01L23/538 , H01L25/065 , H01L23/48
摘要： A de vice and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.

3. 发明申请

WO2018004619A1 HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE 审中-公开
标题翻译：配置用于制造和性能的高密度互连结构
公开(公告)号：WO2018004619A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040486
申请日：2016-06-30
申请人： BRAUNISCH, Henning , AYGUN, Kemal , JAIN, Ajay , QIAN, Zhiguo
发明人： BRAUNISCH, Henning , AYGUN, Kemal , JAIN, Ajay , QIAN, Zhiguo
IPC分类号： H01L23/48 , H01L23/00 , H01L23/495 , H01L23/498 , H01L23/522
摘要： Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
摘要翻译：这里通常讨论的是包括或提供高密度互连结构的方法和设备。高密度互连结构可以包括交替介电层和金属化层的叠层，所述金属化层包括至少三个金属化层，所述至少三个金属化层包括在导电材料之间具有低k介电材料的导电材料，以及至少两个介电层，包括第一介质k介电材料，所述至少两个电介质层位于所述至少三个金属化层的两个金属化层之间，第二介质k电介质材料直接位于所述堆叠的顶表面上，第二通孔延伸穿过所述第二介质k电介质所述第二通孔电连接到所述三个或更多个金属化层的金属化层中的导电材料，所述第二介质k电介质材料上方的焊盘并且电连接到所述第二通孔。

4. 发明申请

WO2017039628A1 INORGANIC INTERPOSER FOR MULTI-CHIP PACKAGING 审中-公开
标题翻译：无芯插件多芯片包装
公开(公告)号：WO2017039628A1
公开(公告)日：2017-03-09
申请号：PCT/US2015/047811
申请日：2015-08-31
申请人： SOBIESKI, Daniel , DARMAWIKARTA, Kristof , BOYAPATI, Sri Ranga Sai , CELIKKOL, Merve , LEE, Kyu Oh , AYGUN, Kemal , QIAN, Zhiguo
发明人： SOBIESKI, Daniel , DARMAWIKARTA, Kristof , BOYAPATI, Sri Ranga Sai , CELIKKOL, Merve , LEE, Kyu Oh , AYGUN, Kemal , QIAN, Zhiguo
IPC分类号： H01L25/065 , H01L25/18
CPC分类号： H01L25/18 , H01L23/147 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H01L2224/16227 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/15313 , H01L2924/157 , H01L2924/3511
摘要： Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.
摘要翻译：这里通常讨论的是包括无机插入物的多芯片封装的方法和装置。器件可以包括其中包括低密度互连电路的衬底，衬底上的无机插入器，无机插入器包括电连接到低密度互连电路的高密度互连电路，无机插入器包括无机材料，以及两个或更多个芯片连接到无机插入器，两个或更多芯片通过高密度互连电路彼此电连接。

5. 发明申请

WO2018063261A1 DIE INTERCONNECT STRUCTURES AND METHODS 审中-公开
标题翻译：模具互连结构与方法
公开(公告)号：WO2018063261A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054550
申请日：2016-09-29
申请人： QIAN, Zhiguo , AYGUN, Kemal
发明人： QIAN, Zhiguo , AYGUN, Kemal
IPC分类号： H01L23/00 , H01L23/12
CPC分类号： H01L23/5383 , H01L23/00 , H01L23/5226 , H01L23/528 , H01L24/14
摘要： Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.
摘要翻译：这里一般讨论的是用于减少串扰干扰的系统，设备和方法。互连结构可以包括第一金属层，第二金属层，第三金属层，第一金属层比第二金属层和第三金属层更靠近第一和第二管芯，第一金属层包括覆盖区内的接地平面互连结构的凸块区域和凸块区域的占位面积之外的信号迹线。

6. 发明申请

WO2018004620A1 BRIDGE DIE DESIGN FOR HIGH BANDWIDTH MEMORY INTERFACE 审中-公开
标题翻译：高带宽存储器接口的桥接模设计
公开(公告)号：WO2018004620A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040490
申请日：2016-06-30
申请人： QIAN, Zhiguo , AYGUN, Kemal , KIM, Dae-Woo , PRECIADO, Jackie C.
发明人： QIAN, Zhiguo , AYGUN, Kemal , KIM, Dae-Woo , PRECIADO, Jackie C.
IPC分类号： H01L23/538 , H01L23/00 , H01L25/065
摘要： A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.
摘要翻译：微电子封装桥接件可以包括多个接地层以及与多个接地层交织的多个信号层。每个信号层可以包括多个导电路径。每个导电路径可以布置成在第一管芯的第一多个凸块中的一个与第二管芯的第二多个凸块中的一个之间形成电连接。多个导电路径中的每一个可以具有基本上彼此相等的长度。

7. 发明申请

WO2013101243A1 HIGH DENSITY PACKAGE INTERCONNECTS 审中-公开
标题翻译：高密度封装互连
公开(公告)号：WO2013101243A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068278
申请日：2011-12-31
申请人： INTEL CORPORATION , GANESAN, Sanka , QIAN, Zhiguo , SANKMAN, Robert L. , SRINIVASAN, Krishna , ZHU, Zhaohui
发明人： GANESAN, Sanka , QIAN, Zhiguo , SANKMAN, Robert L. , SRINIVASAN, Krishna , ZHU, Zhaohui
IPC分类号： H01L21/60
CPC分类号： H01L23/49811 , H01L21/76885 , H01L23/50 , H01L23/5386 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/10126 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/11849 , H01L2224/1301 , H01L2224/13013 , H01L2224/13014 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13562 , H01L2224/1357 , H01L2224/13687 , H01L2224/14132 , H01L2224/14133 , H01L2224/14135 , H01L2224/14136 , H01L2224/16013 , H01L2224/16014 , H01L2224/16058 , H01L2224/16238 , H01L2224/1703 , H01L2224/17051 , H01L2224/81191 , H01L2224/81203 , H01L2224/81385 , H01L2224/81395 , H01L2224/81411 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81815 , H01L2924/05042 , H01L2924/1434 , H01L2924/381 , H01L2924/3841 , H01L2924/014 , H01L2924/00014
摘要： Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.
摘要翻译：描述了包括形成互连结构的电子组件和方法。在一个实施例中，设备包括半导体管芯和管芯上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。描述和要求保护其他实施例。

8. 发明申请

WO2017111823A1 GROUND PLANE VERTICAL ISOLATION OF, GROUND LINE COAXIAL ISOLATION OF, AND IMPEDANCE TUNING OF HORIZONTAL DATA SIGNAL TRANSMISSION LINES ROUTED THROUGH PACKAGE DEVICES 审中-公开
标题翻译：水平数据信号传输线的接地平面垂直隔离，接地线的同轴隔离和阻抗调谐通过封装器件
公开(公告)号：WO2017111823A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000381
申请日：2015-12-26
申请人： INTEL CORPORATION
发明人： ZHANG, Yu, Amos , REGALADO, Gabriel, S. , QIAN, Zhiguo , AYGUN, Kemal
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L23/48 , H01L23/49838 , H01L2224/16225 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H05K1/0218 , H05K1/0219 , H05K1/0243
摘要： A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical, isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.
摘要翻译：接地隔离传输线封装装置包括（1）围绕或（3）这些接地平面周围的接地隔离线与围绕水平数据信号传输的这种接地隔离线之间的接地隔离平面通过封装器件水平布线的线（例如，金属信号迹线）。（1）接地隔离线和/或（2）接地隔离线之间的（1）接地隔离平面电屏蔽信号线中传输的数据信号，从而减少数据信号传输线之间的信号串扰并增加电隔离。另外，可以使用眼图来调谐数据信号传输线以选择提供最佳数据传输性能的信号线宽度和接地隔离线宽度。该封装器件在数据信号传输线的不同水平位置之间提供更高频率和更准确的数据信号传输，并且因此也在诸如附接到封装器件的集成电路（IC）芯片之类的器件之间提供更高频率和更准确的数据信号传输。

9. 发明申请

WO2017111957A1 SEMICONDUCTOR PACKAGE WITH THROUGH BRIDGE DIE CONNECTIONS 审中-公开
标题翻译：半导体封装通过桥接模具连接
公开(公告)号：WO2017111957A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067447
申请日：2015-12-22
申请人： INTEL CORPORATION
发明人： QIAN, Zhiguo , XIE, Jianyong , AYGUN, Kemal
IPC分类号： H01L25/065 , H01L25/07 , H01L23/48
CPC分类号： H01L24/20 , H01L25/065 , H01L25/07 , H01L2224/13111 , H01L2224/13147 , H01L2224/16145 , H01L2224/16237 , H01L2224/73204 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/01029 , H01L2924/014
摘要： Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.
摘要翻译：公开了具有穿通桥芯片连接的半导体封装及其制造方法。半导体封装可以容纳一个或多个电子组件作为封装（SiP）实现中的系统。诸如嵌入式多芯片互连桥（EMIB）之类的桥接管芯可嵌入半导体封装的一个或多个构建层内。桥接管芯可以具有导电块，其可以在背侧电连接到电源平面并且用于经由形成在桥接管芯的顶侧上的互连而将电力递送到附接到半导体封装的一个或多个管芯，电桥到桥模的大部分。与在桥芯片周围路由功率相比，可以实现通过桥芯片传输功率的更直接路径。

10. 发明申请

WO2022132265A1 POWER-FORWARDING BRIDGE FOR INTER-CHIP DATA SIGNAL TRANSFER 审中-公开
公开(公告)号：WO2022132265A1
公开(公告)日：2022-06-23
申请号：PCT/US2021/051521
申请日：2021-09-22
申请人： INTEL CORPORATION
发明人： QIAN, Zhiguo , PASDAST, Gerald , WANG, Peipei , KRUEGER, Daniel , BURTON, Edward
IPC分类号： G11C5/02 , G11C5/06 , G11C7/10
摘要： An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

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