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1. 发明申请

WO2010107571A3 APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE 审中-公开
标题翻译：用于改善量子阱器件中并联导通的装置和方法
公开(公告)号：WO2010107571A3
公开(公告)日：2011-01-06
申请号：PCT/US2010025845
申请日：2010-03-02
申请人： INTEL CORP , PILLARISETTY RAVI , HUDAIT MANTU , JIN BEEN-YIH , CHU-KUNG BENJAMIN , CHAU ROBERT
发明人： PILLARISETTY RAVI , HUDAIT MANTU , JIN BEEN-YIH , CHU-KUNG BENJAMIN , CHAU ROBERT
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66977 , H01L29/1083 , H01L29/161 , H01L29/365 , H01L29/66431 , H01L29/66439 , H01L29/7781
摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
摘要翻译：本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。可以描述和要求保护其他实施例。

2. 发明申请

WO2011090583A3 GERMANIUM-BASED QUANTUM WELL DEVICES 审中-公开
标题翻译：基于锗的量子阱器件
公开(公告)号：WO2011090583A3
公开(公告)日：2011-10-13
申请号：PCT/US2010059620
申请日：2010-12-09
申请人： INTEL CORP , PILLARISETTY RAVI , JIN BEEN-YIH , CHU-KUNG BENJAMIN , METZ MATTHEW V , KAVALIEROS JACK T , RADOSAVLJEVIC MARKO , KOTLYAR ROZA , RACHMADY WILLY , MUKHERJEE NILOY , DEWEY GILBERT , CHAU ROBERT
发明人： PILLARISETTY RAVI , JIN BEEN-YIH , CHU-KUNG BENJAMIN , METZ MATTHEW V , KAVALIEROS JACK T , RADOSAVLJEVIC MARKO , KOTLYAR ROZA , RACHMADY WILLY , MUKHERJEE NILOY , DEWEY GILBERT , CHAU ROBERT
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译：量子阱晶体管具有锗量子阱沟道区域。含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。通道区域上方和下方的分级硅锗层提高性能。多栅极电介质材料允许使用高k值栅极电介质。

3. 发明申请

WO2011075228A2 ISOLATION FOR NANOWIRE DEVICES 审中-公开
标题翻译：纳米器件的隔离
公开(公告)号：WO2011075228A2
公开(公告)日：2011-06-23
申请号：PCT/US2010055225
申请日：2010-11-03
申请人： INTEL CORP , SHAH UDAY , CHU-KUNG BENJAMIN , JIN BEEN-YIH , PILLARISETTY RAVI , RADOSAVLJEVIC MARKO , RACHMADY WILLY
发明人： SHAH UDAY , CHU-KUNG BENJAMIN , JIN BEEN-YIH , PILLARISETTY RAVI , RADOSAVLJEVIC MARKO , RACHMADY WILLY
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译：本公开涉及制造微电子器件的领域。在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构为其上形成微电子结构提供基本上水平的表面。

4. 发明申请

WO2007078892A2 A TENSILE STRAINED NMOS TRANSISTOR USING GROUP III-N SOURCE/DRAIN REGIONS 审中-公开
标题翻译：采用III-N族源/漏区的拉伸应变NMOS晶体管
公开(公告)号：WO2007078892A2
公开(公告)日：2007-07-12
申请号：PCT/US2006048078
申请日：2006-12-15
申请人： INTEL CORP , DATTA SUMAN , BRASK JUSTIN K , JIN BEEN-YIH , KAVALIEROS JACK T , HUDAIT MANTU K
发明人： DATTA SUMAN , BRASK JUSTIN K , JIN BEEN-YIH , KAVALIEROS JACK T , HUDAIT MANTU K
IPC分类号： H01L21/336 , H01L29/10
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/517 , H01L29/66628 , H01L29/7848 , Y10S438/933 , Y10S438/938
摘要： Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
摘要翻译：描述了增强模式晶体管，其中在源极区和漏极区中使用III-N族化合物以在通道上施加拉伸应变。源区和漏区可以被升高或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。

5. 发明申请

WO2009088587A3 METHODS OF FORMING NANODOTS USING SPACER PATTERNING TECHNIQUES AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：使用间隔图案技术形成纳米结构的方法和形成的结构
公开(公告)号：WO2009088587A3
公开(公告)日：2009-09-11
申请号：PCT/US2008085226
申请日：2008-12-02
申请人： INTEL CORP , DOYLE BRIAN , JIN BEEN-YIH , KAVALIEROS JACK , CHAU ROBERT
发明人： DOYLE BRIAN , JIN BEEN-YIH , KAVALIEROS JACK , CHAU ROBERT
IPC分类号： H01L21/027 , B82B3/00
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , Y10T428/24612
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在纳点物质上形成第一块，在第一块上形成第一隔离物，去除第一块以形成自由间隔物，去除纳米点材料的暴露部分，然后除去自由间隔物以形成纳米线，在与所述纳米线的长度成一定角度地形成第二块，在所述第二块上形成第二间隔物，通过去除所述第二块在所述纳米线上形成第二自由间隔物，以及去除所述纳米线的暴露部分，然后除去所述第二自由基形成有序阵列的纳米点。

6. 发明申请

WO2009032576A3 METHOD TO FABRICATE ADJACENT SILICON FINS OF DIFFERING HEIGHTS 审中-公开
标题翻译：制造不同高度的相邻硅片的方法
公开(公告)号：WO2009032576A3
公开(公告)日：2009-05-07
申请号：PCT/US2008074161
申请日：2008-08-25
申请人： INTEL CORP , DOYLE BRIAN S , JIN BEEN-YIH , SHAH UDAY
发明人： DOYLE BRIAN S , JIN BEEN-YIH , SHAH UDAY
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L29/785 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L29/66795
摘要： A method to fabricate adjacent silicon fins of differing heights comprises providing a silicon substrate having an isolation layer deposited thereon, patterning the isolation layer to form first and second isolation structures, patterning the silicon substrate to form a first silicon fin beneath the first isolation structure and a second silicon fin beneath the second isolation structure, depositing an insulating layer on the substrate, planarizing the insulating layer to expose top surfaces of the first and second isolation structures, depositing and patterning a masking layer to mask the first isolation structure but not the second isolation structure, applying a wet etch to remove the second isolation structure and expose the second silicon fin, epitaxially depositing a silicon layer on the second silicon fin, and recessing the insulating layer to expose at least a portion of the first silicon fin and at least a portion of the second silicon fin.
摘要翻译：制造具有不同高度的相邻硅鳍的方法包括：提供其上沉积有隔离层的硅衬底;图案化隔离层以形成第一和第二隔离结构;图案化硅衬底以在第一隔离结构下形成第一硅鳍;以及在所述第二隔离结构下方的第二硅鳍状物，在所述衬底上沉积绝缘层，平坦化所述绝缘层以暴露所述第一和第二隔离结构的顶表面，沉积并图案化掩模层以掩蔽所述第一隔离结构而不是所述第二施加湿蚀刻以去除第二隔离结构并暴露第二硅鳍;在第二硅鳍上外延沉积硅层;以及使绝缘层凹陷以暴露第一硅鳍的至少一部分，并且至少第二硅鳍的一部分。

7. 发明申请

WO2009042981A3 METHOD TO INTRODUCE UNIAXIAL STRAIN IN MULTIGATE NANOSCALE TRANSISTORS BY SELF ALIGNED SI TO SIGE CONVERSION PROCESSES AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：通过自对准SI引入多元纳米晶体管中的单轴应变的方法来标识形成的转换过程和结构
公开(公告)号：WO2009042981A3
公开(公告)日：2009-06-04
申请号：PCT/US2008078041
申请日：2008-09-28
申请人： INTEL CORP , JIN BEEN-YIH , DOYLE BRIAN , KAVALIEROS JACK , DATTA SUMAN
发明人： JIN BEEN-YIH , DOYLE BRIAN , KAVALIEROS JACK , DATTA SUMAN
IPC分类号： H01L29/78 , H01L29/00 , H01L29/80
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7848
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例可以包括提供包括顶表面和第一和第二横向相对的侧壁的栅电极，其中硬掩模设置在顶表面上，源极漏极区域设置在栅电极的相对侧上，在栅电极的第一和第二横向相对的侧壁上，在源漏区的顶表面和第一和第二横向相对的侧壁的暴露部分上形成硅锗层，然后氧化硅锗层的一部分，其中硅锗层的锗部分被迫下降到源极漏极区域中，以将源极区域的硅部分转换成源极漏极区域的硅锗部分。

8. 发明申请

WO2005031827A3 SEMICONDUCTOR CHANNEL ON INSULATOR STRUCTURE 审中-公开
标题翻译：绝缘子结构半导体通道
公开(公告)号：WO2005031827A3
公开(公告)日：2005-05-26
申请号：PCT/US2004031070
申请日：2004-09-23
申请人： INTEL CORP
发明人： JIN BEEN-YIH , DOYLE BRIAN , HARELAND SCOTT , DOCZY MARK , METZ MATTHEW , BOYANOV BOYAN , DATTA SUMAN , KAVALIEROS JACK , CHAU ROBERT
IPC分类号： H01L21/20 , H01L21/336 , H01L21/768 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L29/66742 , H01L29/78603 , H01L29/78648 , H01L29/78681
摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.
摘要翻译：一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包含衍生自所述器件基板的晶体结构。

9. 发明申请

WO2005010997A3 NONPLANAR DEVICE WITH STRESS INCORPORATION LAYER AND METHOD OF FABRICATION 审中-公开
标题翻译：具有应力合并层的非平面装置和制造方法
公开(公告)号：WO2005010997A3
公开(公告)日：2005-03-24
申请号：PCT/US0339727
申请日：2003-12-12
申请人： INTEL CORP
发明人： HARELAND SCOTT , CHAU ROBERT , DOYLE BRIAN , DATTA SUMAN , JIN BEEN-YIH
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/76 , H01L29/786
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
摘要翻译：包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

10. 发明申请

WO2004051712A3 NOVEL FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION 审中-公开
标题翻译：新型场效应晶体管和制造方法
公开(公告)号：WO2004051712A3
公开(公告)日：2004-08-12
申请号：PCT/US0334667
申请日：2003-10-31
申请人： INTEL CORP
发明人： CHAU ROBERT , BARLAGE DOUGLAS , JIN BEEN-YIH
IPC分类号： H01L21/336 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/786 , H01L21/786
CPC分类号： H01L29/4908 , H01L29/458 , H01L29/66643 , H01L29/66742 , H01L29/7839 , H01L29/78681 , H01L29/78684 , H01L29/78696 , Y10S438/936
摘要： The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the narrow bandgap semiconductor film.
摘要翻译：本发明是一种新颖的场效应晶体管，其具有由形成在绝缘基板上的窄带隙半导体膜形成的沟道区。栅极电介质层形成在窄带隙半导体膜上。然后在栅极电介质上形成栅电极。由宽带隙半导体膜或金属形成的一对源极/漏极区域形成在栅电极的相对侧并与窄带隙半导体膜相邻。

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