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1. 发明申请

WO2013095692A3 ELECTRICAL FUSE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：电保险丝及其制造方法
公开(公告)号：WO2013095692A3
公开(公告)日：2013-10-24
申请号：PCT/US2012032040
申请日：2012-04-04
申请人： IBM , YANG CHIH-CHAO , GATES STEPHEN M , LI BAOZHEN , EDELSTEIN DAN
发明人： YANG CHIH-CHAO , GATES STEPHEN M , LI BAOZHEN , EDELSTEIN DAN
IPC分类号： H01L21/82 , H01L21/8242 , H01L23/62 , H01L27/108
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An improved electrical-fuse (e-fuse) device (200) including a dielectric layer (102) having a first top surface (108), two conductive features (104, 106) embedded in the dielectric layer (102) and a fuse element (122). Each conductive feature (104, 106) has a second top surface (110, 112) and a metal cap (114, 116) directly on the second top surface (110, 112). Each metal cap (114, 116) has a third top surface (118, 120) that is above the first top surface (108) of the dielectric layer (102). The fuse element (122) is on the third top surface (118, 120) of each metal cap (114, 116) and on the first top surface (108) of the dielectric layer (102). A method of forming the e-fuse device (200) is also provided.
摘要翻译：一种改进的电熔丝（e熔丝）装置（200），包括具有第一顶表面（108）的介电层（102），嵌在电介质层（102）中的两个导电特征（104,106）和熔丝元件（122）。每个导电特征（104,106）具有直接在第二顶表面（110,112）上的第二顶表面（110,112）和金属盖（114,116）。每个金属帽（114,116）具有在介电层（102）的第一顶表面（108）上方的第三顶表面（118,120）。熔丝元件（122）位于每个金属盖（114,116）的第三顶表面（118,120）上并且位于介电层（102）的第一顶表面（108）上。还提供了形成电熔丝装置（200）的方法。

2. 发明申请

WO2011037710A2 MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY 审中-公开
标题翻译：模块化三维电容阵列
公开(公告)号：WO2011037710A2
公开(公告)日：2011-03-31
申请号：PCT/US2010046267
申请日：2010-08-23
申请人： IBM , HSU LOUIS L , OUYANG XU , YANG CHIH-CHAO
发明人： HSU LOUIS L , OUYANG XU , YANG CHIH-CHAO
IPC分类号： G11C11/24 , G11C11/34
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电连接电容器的开关装置。开关装置包括感测单元，该感测单元被配置为检测电容器的泄漏水平，使得如果泄漏电流超过预定水平，则开关装置电切断电容器。每个电容器模块可以包括单个电容器板，两个电容器板或两个以上的电容器板。采用泄漏传感器和开关装置来电切断电容器阵列中任何变得泄漏的电容器模块，由此保护电容器阵列免于过度的漏电。

3. 发明申请

WO2011032812A1 CONDUCTIVE STRUCTURE FOR NARROW INTERCONNECT OPENINGS 审中-公开
标题翻译：导电结构用于连接开口
公开(公告)号：WO2011032812A1
公开(公告)日：2011-03-24
申请号：PCT/EP2010/062407
申请日：2010-08-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , ROSSNAGEL, Stephen , YANG, Chih-Chao , EDELSTEIN, Daniel , NOGAMI, Takeshi
发明人： ROSSNAGEL, Stephen , YANG, Chih-Chao , EDELSTEIN, Daniel , NOGAMI, Takeshi
IPC分类号： H01L21/768
CPC分类号： H01L21/76871 , H01L21/76846 , H01L21/76868 , H01L21/76883
摘要： An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material (24) including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer (30), a grain growth promotion layer (32), an agglomerated plating seed layer (34'), an optional second plating seed layer a conductive structure (38). The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation.
摘要翻译：提供具有降低的电阻的互连结构和形成这种互连结构的方法。互连结构包括其中包括至少一个开口的电介质材料（24）。所述至少一个开口填充有可选的阻挡扩散层（30），晶粒生长促进层（32），聚集的电镀种子层（34'），任选的第二电镀种子层，导电结构（38）。包含含金属的导电材料（通常为Cu）的导电结构具有竹结构，平均晶粒尺寸大于0.05微米。在一些实施例中，导电结构包括具有（111）晶体取向的导电晶粒。

4. 发明申请

WO2009142655A1 STRUCTURE AND PROCESS FOR CONDUCTIVE CONTACT INTEGRATION 审中-公开
标题翻译：导电接触集成的结构与工艺
公开(公告)号：WO2009142655A1
公开(公告)日：2009-11-26
申请号：PCT/US2008/077375
申请日：2008-09-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-chao , GIGNAC, Lynne M.
发明人： YANG, Chih-chao , GIGNAC, Lynne M.
IPC分类号： H01L21/02 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76862 , H01L21/76864 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity.
摘要翻译：提供了一种半导体结构，其包括消除了键孔形成的高可靠性高纵横比接触结构。在本发明中通过在存在于电介质材料中的高纵横比接触开口内提供致密的含贵金属衬里来消除键孔缝形成。致密化的含贵金属的衬里位于扩散阻挡层的顶部，并且这两个元件将本发明接触结构的导电材料与下面的半导体结构的导电材料分开。通过沉积具有第一电阻率的含贵金属的材料形成本发明的含致密化的含贵金属的衬里，并使沉积的含贵金属的材料经受降低电阻率的致密化处理（热或等离子体）的沉积的含贵金属材料的电阻率较低。

5. 发明申请

WO2009106520A1 BILAYER METAL CAPPING LAYER FOR INTERCONNECT APPLICATIONS 审中-公开
标题翻译：双层金属覆盖层用于互连应用
公开(公告)号：WO2009106520A1
公开(公告)日：2009-09-03
申请号：PCT/EP2009/052160
申请日：2009-02-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , NITTA, Satyanarayana, Venkata , YANG, Chih-Chao
发明人： NITTA, Satyanarayana, Venkata , YANG, Chih-Chao
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76849 , H01L21/76805 , H01L21/76814 , H01L21/76843 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer (76) is located on a surface of a first metallic cap layer (60) which is, in turn, located on a surface of the conductive feature (58) embedded within a first dielectric material (54). Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, which is present within an overlying second dielectric material (68). The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures.
摘要翻译：本发明提供了具有改进的可靠性和技术可扩展性的半导体互连结构。在本发明中，第二金属覆盖层（76）位于第一金属覆盖层（60）的表面上，第一金属覆盖层（60）又位于导电特征（58）的嵌入第一介电材料（54）。第一和第二金属覆盖层都位于开口下方，例如存在于覆盖的第二介电材料（68）内的通孔开口。第二金属覆盖层保护第一介电覆盖层在随后的处理步骤期间被去除（完全或部分地）。公开了包括通过气刨特征以及非通孔气刨功能的互连结构。本发明提供制造这种半导体互连结构的方法。

6. 发明申请

WO2008051674A3 ELECTRICAL FUSE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：电保险丝及其制造方法
公开(公告)号：WO2008051674A3
公开(公告)日：2008-08-28
申请号：PCT/US2007079375
申请日：2007-09-25
申请人： IBM , YANG CHIH-CHAO , YANG HAINING
发明人： YANG CHIH-CHAO , YANG HAINING
IPC分类号： G11C17/14
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a trench feature in a substrate, depositing fuse material in the trench feature and compressive stress liner material over the fuse material, and patterning the compressive stress liner material.
摘要翻译：半导体熔丝包括熔丝元件和减小熔丝元件的电迁移电阻的压应力衬垫。该方法包括在衬底中形成沟槽特征，在沟槽特征中沉积熔丝材料并将压应力衬垫材料沉积在熔丝材料上，以及对压应力衬垫材料进行图案化。

7. 发明申请

WO2008091558A1 HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT 审中-公开
标题翻译：混合互连结构，用于性能改进和可靠性增强
公开(公告)号：WO2008091558A1
公开(公告)日：2008-07-31
申请号：PCT/US2008/000740
申请日：2008-01-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-Chao , SHAW, Thomas, M. , WONG, Keith, Kwong, Hon , YANG, Haining, S.
发明人： YANG, Chih-Chao , SHAW, Thomas, M. , WONG, Keith, Kwong, Hon , YANG, Haining, S.
IPC分类号： H01L23/48
CPC分类号： H01L21/76841 , H01L21/7682 , H01L21/76831 , H01L23/481 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.
摘要翻译：本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地，气隙。与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

8. 发明申请

WO2008036115A1 NOVEL STRUCTURE AND METHOD FOR METAL INTEGRATION 审中-公开
标题翻译：金属整合的新结构和方法
公开(公告)号：WO2008036115A1
公开(公告)日：2008-03-27
申请号：PCT/US2007/005414
申请日：2007-03-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-chao , SPOONER, Terry, A. , VAN DER STRATEN, Oscar
发明人： YANG, Chih-chao , SPOONER, Terry, A. , VAN DER STRATEN, Oscar
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/02063 , H01L21/31105 , H01L21/31144 , H01L21/32131 , H01L21/76805 , H01L21/76808 , H01L21/76814 , H01L21/76843 , H01L21/76844 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings. In accordance with the present invention, such an interconnect structure is achieved by providing the gouging feature in the bottom of the via opening prior to formation of the line opening and deposition of the diffusion barrier in said line opening.
摘要翻译：提供了包括在一个通孔开口的底部的气泡特征的互连结构及其形成方法。根据本发明，形成互连结构的方法不会破坏上覆线路开口中沉积的扩散阻挡层的覆盖，也不会引起由Ar溅射引起的包括通孔和线路开口的介电材料的损伤。根据本发明，这种互连结构仅在通孔开口内包含扩散阻挡层，但不包括在上覆开口中。该特征增强了通孔开口区域周围的机械强度和扩散性能，而不会降低线路开口内导体的体积分数。根据本发明，通过在形成线路开口和扩散阻挡层在所述线路开口中的沉积之前，在通孔开口的底部提供气泡特征来实现这种互连结构。

9. 发明申请

WO2007137969A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING HIGH-Q WAFER BACK-SIDE CAPACITORS 审中-公开
标题翻译：具有高Q波形背面电容器的半导体集成电路器件
公开(公告)号：WO2007137969A1
公开(公告)日：2007-12-06
申请号：PCT/EP2007/054941
申请日：2007-05-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CLEVENGER, Lawrence , DALTON, Timothy, Joseph , HSU, Louis, Lu-Chen , RADENS, Carl, John , RAMACHANDRAN, Vidhya , WONG, Keith, Kwong Hon , YANG, Chih-Chao
发明人： CLEVENGER, Lawrence , DALTON, Timothy, Joseph , HSU, Louis, Lu-Chen , RADENS, Carl, John , RAMACHANDRAN, Vidhya , WONG, Keith, Kwong Hon , YANG, Chih-Chao
IPC分类号： H01L21/8242 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semico nductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

10. 发明申请

WO2012170142A2 SEMICONDUCTOR SWITCHING DEVICE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：半导体开关器件及其制造方法
公开(公告)号：WO2012170142A2
公开(公告)日：2012-12-13
申请号：PCT/US2012/037212
申请日：2012-05-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-Chao , COHEN, Stephan, A. , BAOZHEN, Li
发明人： YANG, Chih-Chao , COHEN, Stephan, A. , BAOZHEN, Li
IPC分类号： H01L29/00 , H01L21/8238 , H01L21/205
CPC分类号： B82Y10/00 , H01L23/5252 , H01L29/413 , H01L2924/0002 , H01L2924/00
摘要： A switching device (140 or 240) including a first dielectric layer (102 or 207) having a first top surface (108 or 218), two conductive features (104, 106 or 214, 216) embedded in the first dielectric layer (102 or 207), each conductive feature (104, 106 or 214, 216) having a second top surface (110, 112 or 220, 222) that is substantially coplanar with the first top surface (108 or 218) of the first dielectric layer (102 or 207), and a set of discrete islands of a low diffusion mobility metal (114a-c or 204a-c) between the two conductive features (104, 106 or 214, 216). The discrete islands of the low diffusion mobility metal (114a-c or 204a-c) may be either on the first top surface (108) or embedded in the first dielectric layer (207). The electric conductivity across the two conductive features (104, 106 or 214, 216) of the switching device (140 or 240) increases when a prescribed voltage is applied to the two conductive features (104, 106 or 214, 216). A method of forming such a switching device (140 or 240) is also provided.
摘要翻译：一种包括具有第一顶表面（108或218）的第一介电层（102或207），嵌入第一介电层（102或210）中的两个导电特征（104,106或214,216）的开关装置（140或240）每个导电特征（104,106或214,216）具有与第一介电层（102）的第一顶表面（108或218）基本上共面的第二顶表面（110,112或220,222）或207），以及一组在两个导电特征（104,106或214,216）之间的低扩散迁移率金属（114a-c或204a-c）的离散岛。低扩散迁移率金属（114a-c或204a-c）的离散岛可以在第一顶表面（108）上或嵌入在第一介电层（207）中。当规定的电压施加到两个导电特征（104,106或214,216）时，开关装置（140或240）的两个导电特征（104,106或214,216）的电导率增加。还提供了一种形成这种开关装置（140或240）的方法。

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