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1. 发明申请

WO1990016123A1 MODEM CAPABLE OF DETECTING OUT-OF-FRAME SYNCHRONISM CONDITION 审中-公开
标题翻译：检测帧外同步状态的调制解调器
公开(公告)号：WO1990016123A1
公开(公告)日：1990-12-27
申请号：PCT/JP1990000769
申请日：1990-06-13
申请人： FUJITSU LIMITED , MIZUTANI, Yasunao , KAKU, Takashi
发明人： FUJITSU LIMITED
IPC分类号： H04L07/08
CPC分类号： H04L27/38 , H04L7/048
摘要： A modem comprising error control encoder means (16) which adds redundancy according to a predetermined procedure to a transmission bit sequence from bit processing means (10) on the transmitting side (1) and encodes them; data sequence-to-coordinate conversion means (18) which converts a bit sequence from said error control encoder means (16) into a signal point coordinate on a complex plane; coordinate rotating means (20) that rotates said converted signal point coordinate based on frame phase data from said frame phase generating means (12); coordinate rotating means (34) which rotates the reception point coordinate reversely to that of the coordinate rotating means (20) on the transmitting side based on the frame phase data of frame phase generating means (28) of the receiving side; second judging means (38) that judges the signal point of the maximum likelihood and corrects error in the reception point coordinate by utilizing the redundancy added by the error control encoder means (16) of the transmitting side; and judging means (40) which judges the presence or absence of an out-of-frame synchronism condition based on a distance between a judging point by said second judging means (38) and a demodulation reception point on the complex plane; wherein out-of-frame synchronism is quickly detected. In the modem, furthermore, values for evaluation are set for the transition series of the signals, the transition series of received signals of the maximum likelihood is selected based on the evaluation values renewed for each reception of signal on the receiving side, error control signal is decoded to correct error at a demodulated signal point, and error is corrected in the data transmission.

2. 发明申请

WO1984000090A1 TRAINING SYSTEM FOR DATA RECEIVER 审中-公开
标题翻译：数据接收机培训系统
公开(公告)号：WO1984000090A1
公开(公告)日：1984-01-05
申请号：PCT/JP1983000191
申请日：1983-06-15
申请人： FUJITSU LIMITED , KAKU, Takashi
发明人： FUJITSU LIMITED
IPC分类号： H04B01/76
CPC分类号： H04L7/10 , H04L25/03133 , H04L2025/03783
摘要： After a transmitter transmits training signals (TR1, TR10, TR11) of lengths corresponding to its own channels and information (i) representing the length of each signal, it transmits a data signal (data), and a receiver trains itself with the received training signals (TR1, TR10, TR11), detects a switching time point between the signal (TR1, TR10, TR11) and the data signal (data) using the length information (i), to train the data receiver by the training signal of the optimum length.

3. 发明申请

WO1983002373A1 AUTOMATIC EQUALIZER AND METHOD OF INITIALIZATION THEREOF 审中-公开
标题翻译：自动均衡器及其初始化方法
公开(公告)号：WO1983002373A1
公开(公告)日：1983-07-07
申请号：PCT/JP1982000479
申请日：1982-12-28
申请人： FUJITSU LIMITED , KAKU, Takashi , UNAGAMI, Shigeyuki , INOUE, Masayoshi
发明人： FUJITSU LIMITED
IPC分类号： H04B03/10
CPC分类号： H04L25/03133
摘要： Un égaliseur automatique reçoit un signal prédéterminé, en extrait un train d'impulsions correspondant à un signal d'impulsion simple comprenant la distorsion provoquée par une ligne de transmission, et initialise un coefficient de branchement en utilisant le train d'impulsions extrait. Le dispositif comprend deux circuits égaliseurs, dont le premier (23) détermine un coefficient de branchement en fonction d'un train qui est un conjugué du train d'impulsions et le deuxième (24) détermine un coefficient de branchement en calculant une matrice inversée d'un train d'auto-corrélation du train d'impulsions.

4. 发明申请

WO1990016117A1 SYSTEM FOR REMOVING CIRCUIT SIGNAL DETERIORATION 审中-公开
标题翻译：移除电路信号检测系统
公开(公告)号：WO1990016117A1
公开(公告)日：1990-12-27
申请号：PCT/JP1990000735
申请日：1990-06-06
申请人： FUJITSU LIMITED , KAKU, Takashi , KISHIMOTO, Hiroki , HIRAO, Kyoko
发明人： FUJITSU LIMITED
IPC分类号： H04B03/06
CPC分类号： H04L27/2332 , H04L1/205 , H04L2027/003 , H04L2027/0057
摘要： A system for removing circuit deterioration components such as intersymbol interference, carrier frequency offset, phase jitter, etc., from the received signals. Signal deterioration caused by intersymbol interference is corrected by automatic equalizing means (10). Then, signal deterioration caused by carrier frequency offset is corrected by carrier phase control means (12). Thereafter, the phase jitter components only are increased by phase jitter interference removing means (18) utilizing the circuit characteristics in order to facilitate the pick up of the phase jitter components. Signals including a phase jitter have a low frequency and are shifted to a high-frequency band on a frequency axis by phase jitter removing means (14) to remove phase jitter on a band where the signals can be easily handled.

5. 发明申请

WO1998018084A1 DEVICE AND METHOD FOR ACCELERATING MEMORY ACCESS SPEED 审中-公开
标题翻译：用于加速存储器访问速度的装置和方法
公开(公告)号：WO1998018084A1
公开(公告)日：1998-04-30
申请号：PCT/JP1997003784
申请日：1997-10-20
申请人： FUJITSU LIMITED , AOKI, Masaki , MORISHIMA, Masahito
发明人： FUJITSU LIMITED
IPC分类号： G06F17/16
CPC分类号： G06F8/4442 , G06F8/447 , G06F9/383
摘要： When the processor of a vector computer detects an optimization instructing message which instructs the optimization of the method for performing access to a list at compiling time, the processor automatically changes the method for accessing. The bank contention associated with vectorization can be avoided and the access speed to the list can be accelerated by, for example, copying the data to be accessed in a working array, randomly changing the accessing order, or performing scalar loading.
摘要翻译：当向量计算机的处理器检测到指示在编译时对表进行访问的方法进行优化的优化指示消息时，处理器自动改变访问方法。可以避免与矢量化相关联的银行争用，并且可以通过例如在工作阵列中复制要访问的数据，随机改变访问顺序或执行标量加载来加速列表的访问速度。

6. 发明申请

WO1998006177A1 COMBINED LOGIC GATE AND LATCH 审中-公开
标题翻译：组合逻辑门和锁
公开(公告)号：WO1998006177A1
公开(公告)日：1998-02-12
申请号：PCT/US1997013618
申请日：1997-08-05
申请人： FUJITSU LIMITED
发明人： FUJITSU LIMITED , ASATO, Creighton
IPC分类号： H03K19/017
CPC分类号： H03K3/356113 , H03K3/037
摘要： A circuit (300) combines the functions of a logic gate (310, 320) and a latch (330) to lower steady state power dissipation during gate operation. The circuit operates in two modes, a flow-through mode and a latched node. In the flow-through mode, a gate portion (310) which receives one or more digital input signals (X1-XN) implements the complement of a desired Boolean logic function on the input signals and provides an internal signal. The gate portion may have a steady-state power dissipation while providing the internal signal. An inverter (350) in a latch portion (330) of the circuit inverts the internal signal to generate an output signal (Z) which represents the desired logical combination of the input signals. The inverter provides the output signal with a full-range CMOS voltage. In latched mode, the gate portion is disabled to stop the steady-state power dissipation while the latch portion of the circuit preserves the desired output signal.
摘要翻译：电路（300）将逻辑门（310,320）和锁存器（330）的功能组合以在门操作期间降低稳态功率耗散。电路工作在两种模式，即流通模式和锁存节点。在流通模式中，接收一个或多个数字输入信号（X1-XN）的门部分（310）在输入信号上实现所需的布尔逻辑函数的补码并提供内部信号。栅极部分可以具有稳态功率耗散，同时提供内部信号。电路的锁存部分（330）中的反相器（350）使内部信号反相以产生表示输入信号的期望逻辑组合的输出信号（Z）。逆变器为输出信号提供全范围CMOS电压。在锁存模式下，禁止门极部分停止稳态功耗，同时电路的锁存部分保留所需的输出信号。

7. 发明申请

WO1998002919A1 METHOD AND MOLD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MOUNTING THE DEVICE 审中-公开
标题翻译：用于制造半导体器件的方法和模具，半导体器件以及用于安装器件的方法
公开(公告)号：WO1998002919A1
公开(公告)日：1998-01-22
申请号：PCT/JP1997002405
申请日：1997-07-10
申请人： FUJITSU LIMITED , FUKASAWA, Norio , KAWAHARA, Toshimi , MORIOKA, Muneharu , OSAWA, Mitsunada , SHINMA, Yasuhiro , MATSUKI, Hirohisa , ONODERA, Masanori , KASAI, Junichi , MARUYAMA, Shigeyuki , SAKUMA, Masao , SUZUKI, Yoshimi , TAKENAKA, Masashi
发明人： FUJITSU LIMITED
IPC分类号： H01L21/56
CPC分类号： H01L21/568 , B29C43/18 , B29C2043/3444 , B29C2043/3628 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/566 , H01L21/6835 , H01L23/24 , H01L23/3107 , H01L23/3114 , H01L23/3121 , H01L23/3128 , H01L23/49572 , H01L23/4985 , H01L24/27 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L29/0657 , H01L2221/68345 , H01L2221/68377 , H01L2224/02371 , H01L2224/0401 , H01L2224/0556 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/274 , H01L2224/29111 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/50 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/83101 , H01L2224/83102 , H01L2224/83191 , H01L2224/85001 , H01L2224/92125 , H01L2224/97 , H01L2225/06517 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06572 , H01L2225/06579 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L2225/1005 , H01L2225/1064 , H01L2225/107 , H01L2225/1082 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0133 , H01L2924/12042 , H01L2924/15153 , H01L2924/15165 , H01L2924/15173 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/15331 , H01L2924/16195 , H01L2924/181 , H01L2924/18161 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2224/85 , H01L2924/00 , H01L2924/01028 , H01L2924/3512 , H01L2224/81 , H01L2924/00012 , H01L2224/05552 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing semiconductor devices includes a resin sealing step of putting a substrate (16) on which bumps (12) and a plurality of semiconductor chips (11) are arranged in the cavity (28) of a mold (20) and supplying a resin (35) to the region where the bumps (12) are provided so as to coat the bumps (12) and form a resin layer (13), a protruded electrode exposing step of exposing at least the front end sections of the bumps (12) coated with the resin layer (13) from the layer (13), and a separating step of separating the semiconductor chips (11) into individual chips (11) by cutting the substrate (16) together with the layer (13).
摘要翻译：一种制造半导体器件的方法包括：树脂密封步骤，将在所述模具（20）的空腔（28）中布置有凸块（12）和多个半导体芯片（11）的基板（16）树脂（35）到设置有凸块（12）的区域，以涂覆凸块（12）并形成树脂层（13）;突出电极暴露步骤，至少暴露凸块的前端部分 12），以及通过与衬底（13）一起切割衬底（16）将半导体芯片（11）分离成单个芯片（11）的分离步骤。

8. 发明申请

WO1997022090A1 NOTE/CARD HANDLING APPARATUS 审中-公开
标题翻译：注/卡处理装置
公开(公告)号：WO1997022090A1
公开(公告)日：1997-06-19
申请号：PCT/JP1996003589
申请日：1996-12-06
申请人： FUJITSU LIMITED , MUKAI, Masanori
发明人： FUJITSU LIMITED
IPC分类号： G07D07/00
CPC分类号： G07D11/0066 , G07D7/00
摘要： A note/card handling apparatus capable of instantaneously reporting the detection of forged cards/notes to a managing personnel, wherein received cards/notes are classified into a first kind likely to be genuine, a second kind likely to be forged, and a third kind less likely to be genuine than the first kind and less likely to be forged than the second kind, and if a predetermined number of notes/cards of the second kind are detected, warning information is issued.
摘要翻译：一种能够立即向管理人员报告伪造卡/票据的检测的便签/卡处理装置，其中接收到的卡片/笔记被分类为可能是真实的第一种，可能被伪造的第一种，第三类不太可能比第一种真伪，并且不太可能被伪造，并且如果检测到第二种类型的预定数量的票据/卡，则发出警告信息。

9. 发明申请

WO1996033239A1 POLYIMIDE RESIN COMPOSITION 审中-公开
标题翻译：聚酰亚胺树脂组合物
公开(公告)号：WO1996033239A1
公开(公告)日：1996-10-24
申请号：PCT/JP1996001045
申请日：1996-04-17
申请人： NIPPON ZEON CO., LTD. , FUJITSU LIMITED , TANAKA, Akira , TAZAKI, Satoshi , YONEDA, Yasuhiro , YOKOUCHI, Kishio
发明人： NIPPON ZEON CO., LTD. , FUJITSU LIMITED
IPC分类号： C08L79/08
CPC分类号： G03F7/0387 , C08G73/1025 , C08K5/3472 , H05K3/285 , C08L79/08
摘要： A polyimide resin composition having an excellent rustproofing effect on copper and its alloys, characterized by comprising a polyimide resin (A) and at least one 1H-tetrazole (B) selected from the group consisting of 1H-tetrazole, 5,5'-bis-1H-tetrazole and derivatives thereof.
摘要翻译：一种对铜及其合金具有优异防锈效果的聚酰亚胺树脂组合物，其特征在于包含聚酰亚胺树脂（A）和至少一种选自1H-四唑5,5'-双 -1H-四唑及其衍生物。

10. 发明申请

WO1995032486A1 PAPER SHEET HANDLING APPARATUS AND PAPER SHEET TRANSACTING APPARATUS 审中-公开
标题翻译：纸张处理设备和纸张交易设备
公开(公告)号：WO1995032486A1
公开(公告)日：1995-11-30
申请号：PCT/JP1995000799
申请日：1995-04-24
申请人： FUJITSU LIMITED , KIMURA, Atsunori , ONO, Yoichi , MINAMISHIN, Hayato , TANAKA, Yuji , OHNO, Seiichi , HATA, Hidekazu , UEDA, Hiroyuki , ESAKI, Isamu , UCHIDA, Atsushi
发明人： FUJITSU LIMITED
IPC分类号： G07D13/00
CPC分类号： G07D11/0018 , B65H83/025 , G07D11/0003 , G07D11/0021 , G07D11/0081 , Y10S209/90
摘要： An apparatus for handling paper sheets such as bank notes, and a paper sheet transacting apparatus, which comprise a discharge unit adapted to carry out feeding and discharging of paper sheets and to be turned between a paper sheet feeding position and a paper sheet ejection position, a partitioning means adapted to project into and retract from the discharge unit and distinguish when it projects the paper sheets fed into the discharge unit from those to be returned, a storage unit for storing paper sheets therein, a temporary storage unit for temporarily storing paper sheets which should not be stored in the storage unit or the paper sheets which should not be discharged, and a plurality of cassettes adapted to carry out the supplying and recovering of paper sheets in the storage unit and the supplying and recovering of paper sheets in the feed and discharge unit. The paper sheet handling apparatus and a paper sheet transacting apparatus rarely fail, and can be operated for a long period of time without being stopped even when a trouble occurs.
摘要翻译：一种用于处理诸如纸币的纸张和纸张交易装置的装置，其包括适于执行纸张的进给和排出并在纸张供给位置和纸张排出位置之间转动的排出单元，分隔装置，其适于投射到排出单元中并从排出单元缩回，并且在将进给到排出单元中的纸张从被返回的纸张伸出时被区分开，用于在其中存储纸张的存储单元，用于临时存储纸张的临时存储单元不应该将其存放在不应放出的存储单元或纸张中，以及适于执行在存储单元中的纸张的供给和回收以及供给和回收进给中的纸张的多个盒和放电单元。纸张处理装置和纸张交易装置很少失败，并且即使发生故障也可以长时间地操作而不停止。

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