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1. 发明申请

WO2012131435A1 APPARATUS FOR FORWARD WELL BIAS IN A SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：用于在半导体集成电路中进行正向漂移的装置
公开(公告)号：WO2012131435A1
公开(公告)日：2012-10-04
申请号：PCT/IB2011/051360
申请日：2011-03-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton , TZYTKIN, Dov
发明人： PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton , TZYTKIN, Dov
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0629 , H01L27/0928
摘要： There is provided a semiconductor Integrated Circuit device having forward well biasing, in which at least one protection device is connected between a supply voltage (Vdd/Vss) and a forward well bias voltage (pwb/nwb).
摘要翻译：提供了具有正向阱偏压的半导体集成电路器件，其中至少一个保护器件连接在电源电压（Vdd / Vss）和正向阱偏置电压（pwb / nwb）之间。

2. 发明申请

WO2013128234A1 METHOD OF DETECTING IRREGULAR CURRENT FLOW IN AN INTEGRATED CIRCUIT DEVICE AND APPARATUS THEREFOR 审中-公开
标题翻译：检测集成电路装置中的非正常电流的方法及其装置
公开(公告)号：WO2013128234A1
公开(公告)日：2013-09-06
申请号：PCT/IB2012/050899
申请日：2012-02-27
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , FLESHEL, Leonid , PRIEL, Michael , WEIZMAN, Yoav
发明人： ROZEN, Anton , FLESHEL, Leonid , PRIEL, Michael , WEIZMAN, Yoav
IPC分类号： G01R19/165 , G01R31/28
CPC分类号： G01N21/66 , G01R15/24 , G01R31/311
摘要： A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.
摘要翻译：描述了在集成电路（IC）装置内检测不规则高电流的方法。该方法包括：至少部分地基于获得的IR发射信息，获得IC器件的红外（IR）发射信息，识别包括高电流的IC器件内的至少一个功能部件，获得至少一个参考部件，以及至少部分地基于用于至少一个功能部件的至少一个功能部件的相应IR发射信息的比较来确定所述至少一个功能部件的高电流是否包括不规则高电流一个参考组件。

3. 发明申请

WO2011064626A1 METHOD FOR COMPENSATING A TIMING SIGNAL, AN INTEGRATED CIRCUIT AND ELECTRONIC DEVICE 审中-公开
标题翻译：用于补偿定时信号，集成电路和电子设备的方法
公开(公告)号：WO2011064626A1
公开(公告)日：2011-06-03
申请号：PCT/IB2009/055421
申请日：2009-11-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
发明人： PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
IPC分类号： G11C11/4096 , G11C11/4093
CPC分类号： G06F1/12 , G11C7/1051 , G11C7/1066
摘要： A method (700, 1000) for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states (720, 1020), identifying state transitions between the current set of data states and the next set of data states (730, 1030, 1040), determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states (750, 1060), and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states (760, 1070).
摘要翻译：一种用于补偿定时信号的方法（700,1000），其中至少一个数据信号的数据状态的输出被同步。该方法包括接收当前数据状态集合和下一组数据状态（720,1020），识别当前数据状态集合与下一组数据状态（730,1030,1040）之间的状态转换，确定一个至少部分地基于在当前数据状态集合和下一组数据状态（750,1060）之间识别的状态转换来应用于定时信号的补偿量，并将确定的补偿量应用于定时信号，如该补偿适用于输出下一组数据状态（760,1070）。

4. 发明申请

WO2011117670A1 INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND METHOD FOR CONFIGURING A SIGNAL PATH FOR A TIMING SENSITIVE SIGNAL 审中-公开
标题翻译：集成电路，电子设备和用于配置时序敏感信号的信号路径的方法
公开(公告)号：WO2011117670A1
公开(公告)日：2011-09-29
申请号：PCT/IB2010/051229
申请日：2010-03-22
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
发明人： PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： G06F1/10
摘要： An integrated circuit (205) comprising at least one signal path (300) for a timing sensitive signal. At least one section (305, 310) of the signal path (300) comprises a first section path (320, 360) comprising a first propagation timing factor, at least one further section path (330, 370) comprising a second propagation timing factor different to the first propagation timing factor, and a path selection component (340, 380) arranged to enable the selection of one of the first and at least one further section paths (320, 330, 360, 370) via which the timing sensitive signal is to propagate through the at least one section (305, 310) of the signal path (300) based on at least one from a group consisting of: the first propagation timing factor, second propagation timing factor.
摘要翻译：一种集成电路（205），包括用于定时敏感信号的至少一个信号路径（300）。信号路径（300）的至少一个部分（305,310）包括包括第一传播定时因子的第一部分路径（320,360），包括第二传播定时因子的至少一个另外的部分路径（330,370）与第一传播定时因子不同的路径选择部件（340,380）被布置成能够选择第一和至少一个另外的部分路径（320,330,360,370）之一，通过该路径选择部件基于来自以下的组中的至少一个来传播信号路径（300）的至少一个部分（305,310）：第一传播定时因子，第二传播时序因子。

5. 发明申请

WO2013179089A1 SEQUENTIAL LOGIC CIRCUIT AND METHOD OF PROVIDING SETUP TIMING VIOLATION TOLERANCE THEREFOR 审中-公开
标题翻译：顺序逻辑电路及其提供设置时序违反的方法
公开(公告)号：WO2013179089A1
公开(公告)日：2013-12-05
申请号：PCT/IB2012/052700
申请日：2012-05-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
发明人： PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
IPC分类号： H03K19/173 , H03K21/16
CPC分类号： H03K19/0016 , H03K5/135 , H03K19/00323 , H03K19/00369 , H03K19/173
摘要： A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby comprising a first logical state. The sequential logic circuit is arranged to operate in at least a first operating mode in which the data input of the first latch component and the data input of the second latch component are operably coupled to a first input of the sequential logic circuit, and in which the clock signals provided to the first and second latch components are such that a transition of the second latch component from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component from a transparent state to a latched state for a time period for receiving late data.
摘要翻译：一种顺序逻辑电路，包括：第一锁存器组件，包括布置成接收输入信号的数据输入;布置成输出第一锁存器组件的当前逻辑状态的数据输出和布置成接收时钟信号的时钟输入; 所述第一锁存部件被布置为在接收到的所述时钟信号时包括透明状态，由此包括第一逻辑状态，并且包括在接收到的所述时钟信号的锁存状态，由此包括第二逻辑状态，以及包括数据输入的第二锁存部件布置成接收输入信号，数据输出可操作地耦合到顺序逻辑电路的输出并且被布置成输出第二锁存部件的当前状态和布置成接收时钟信号的时钟输入; 所述第二锁存器组件被布置为在接收到的所述时钟信号后包括透明状态，由此包括第二逻辑状态，并且包括在接收到的所述时钟信号时的锁存状态，由此包括第一逻辑状态。顺序逻辑电路被布置为在至少第一操作模式中操作，其中第一锁存部件的数据输入和第二锁存部件的数据输入可操作地耦合到顺序逻辑电路的第一输入，并且其中提供给第一和第二锁存部件的时钟信号使得第二锁存部件从透明状态到锁存状态的转变相对于第一锁存部件从透明状态到锁存状态的对应转变而延迟，接收延迟数据的时间段。

6. 发明申请

WO2012069880A1 AN INTEGRATED CIRCUIT AND A METHOD OF POWER MANAGEMENT OF AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路的集成电路和集成电路的电源管理方法
公开(公告)号：WO2012069880A1
公开(公告)日：2012-05-31
申请号：PCT/IB2010/055415
申请日：2010-11-25
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , FLESHEL, Leonid , PRIEL, Michael
发明人： ROZEN, Anton , FLESHEL, Leonid , PRIEL, Michael
IPC分类号： G06F1/26 , G06F13/14
CPC分类号： H03K17/16 , G06F1/3287 , Y02D10/171 , Y02D50/20
摘要： An integrated circuit (2) includes a plurality of power gating elements (14 - 16) for controlling power applied to a first module (4) which is in a powered off state, while a second module (6) is in a powered on state, the second module (6) being coupled to receive at least one signal from the first module (4) when the first module is powered on. Each power gating element (14 - 16) is coupled to a synchronization controller (10) for controlling the power gating elements (14 - 16) to ramp up the power gated to the first module (4) in order to power it up and, for a time while the power gated to the first module (4) is below a first level, reducing the power gated to the second module (6), and for a time when the power gated to the first module (4) is above the first level, increasing the power gated to the second module (6).
摘要翻译：集成电路（2）包括多个电源门控元件（14-16），用于控制施加到处于断电状态的第一模块（4）的电力，而第二模块（6）处于通电状态，所述第二模块（6）被耦合以在所述第一模块通电时从所述第一模块（4）接收至少一个信号。每个电源门控元件（14-16）耦合到同步控制器（10），用于控制功率门控元件（14-16）以使门控到第一模块（4）的功率升高，以向其供电，一旦所述第一模块（4）门控的电力低于第一电平，则减小门控到第二模块（6）的电力，并且在第一模块（4）的电源高于所述第一模块第一级，增加选通第二模块的功率（6）。

7. 发明申请

WO2011154778A1 ELECTRONIC CIRCUIT AND METHOD FOR STATE RETENTION POWER GATING 审中-公开
标题翻译：电子电路和状态保持功率增益的方法
公开(公告)号：WO2011154778A1
公开(公告)日：2011-12-15
申请号：PCT/IB2010/052613
申请日：2010-06-11
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
发明人： PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
IPC分类号： H03K3/356 , H03K19/003 , G06F1/04
CPC分类号： H03K3/00 , H03K3/012 , H03K19/0008
摘要： A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit via the second power grid; and storing, by the SRPG state information.
摘要翻译：一种方法和电子电路，所述方法包括：向切换电路发送状态保持电源选通（SRPG）电路和向第一电源发送指示SRPG电路应以功能模式工作的控制信号; 由开关电路将第三电网耦合到第一电网; 通过第一电网，开关电路和第三电网从第一电源向SRPG电路供电; 经由第二电网从第二电源向第二电路供电; 向SRPG电路和第一电源发送指示SRPG电路在状态保持模式下工作的控制信号; 由开关电路将第三电网耦合到第二电网; 通过第二电网，开关电路和第三电网从第二电源向SRPG电路供电; 经由所述第二电网从所述第二电源向所述第二电路供电; 并通过SRPG状态信息存储。

8. 发明申请

WO2011064624A1 BYPASS CAPACITOR CIRCUIT AND METHOD OF PROVIDING A BYPASS CAPACITANCE FOR AN INTEGRATED CIRCUIT DIE 审中-公开
标题翻译：旁路电容器电路和为集成电路提供旁路电容的方法
公开(公告)号：WO2011064624A1
公开(公告)日：2011-06-03
申请号：PCT/IB2009/055418
申请日：2009-11-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
发明人： PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
IPC分类号： H01L27/108 , H01L21/8242 , G11C11/24 , G11C11/34
CPC分类号： H01L23/5223 , G11C2029/5002 , H01L22/14 , H01L22/22 , H01L23/49589 , H01L23/5286 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A bypass capacitor circuit (30) for an integrated circuit (IC) comprises one or more capacitive devices (32, 34, 36), each arranged in a segment of a seal ring area (16) of a die (12), which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing (66) a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging (68) one or more capacitive devices in a seal ring area of at least one of the IC; dicing (70) the semiconductor wafer device; in a test mode, for each (72) of the one or more capacitive devices, enabling (74) the capacitive device, determining (76) an operability parameter value indicative of an operability of the capacitive device, and storing (78) the operability parameter in a memory device; and in a normal operation mode, providing (80) a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.
摘要翻译：用于集成电路（IC）的旁路电容器电路（30）包括一个或多个电容器件（32,34,36），每个电容器件布置在管芯（12）的密封环区域（16）的段中，其包括 IC。提供用于IC的旁路电容的方法包括提供（66）包括多个芯片的半导体晶片装置，每个芯片包括IC; 在所述IC中的至少一个的密封环区域中布置（68）一个或多个电容性器件; 切割（70）半导体晶片装置; 在测试模式下，对于一个或多个电容性装置中的每个（72），启用（74）电容性装置，确定（76）表示电容性装置的可操作性的可操作性参数值，并且存储（78）可操作性参数; 并且在正常操作模式中，根据具有指示对应的电容性装置的非缺陷性的相关联的可操作性参数值的一个或多个电容性装置的电容，向IC提供（80）旁路电容。

9. 发明申请

WO2014108740A1 ELECTRONIC DEVICE AND METHOD FOR STATE RETENTION 审中-公开
标题翻译：用于状态保持的电子设备和方法
公开(公告)号：WO2014108740A1
公开(公告)日：2014-07-17
申请号：PCT/IB2013/050178
申请日：2013-01-09
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , KUZMIN, Dan
发明人： PRIEL, Michael , FLESHEL, Leonid , KUZMIN, Dan
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318555 , G01R31/318558 , G01R31/318575 , G06F1/3243 , G06F1/3275 , G06F3/0625 , G06F3/064 , G06F3/0653 , G06F9/3869 , G06F11/1402 , G06F13/14 , G06F13/38 , G11C7/1036 , G11C19/28
摘要： An electronic device (10) comprising a set of two or more scan chains (C0, C1) and a memory unit (MEM) is described. Each of the scan chains (C0, C1) has an input end and an output end, which are opposite ends of the respective scan chain, and each of the scan chains (C0, C1, C2) comprises a sequence of stateful elements (F3, F2, F1, F0) connected in series between the input end and the output end, and each of the scan chains (C0, C1) is arranged to hold a string (ABCDEFGH; IJKLMN) having a length identical to the length of the respective scan chain (C0; C1), namely identical to the number of stateful elements of the chain. The strings of the scan chains (C0, C1 ) are shifted in parallel from the scan chains (C0, C1) into the memory unit (MEM) via the respective output ends in a store operation (S1— S8) and back from the memory unit (MEM) into the respective scan chains (C0, C1) via the respective input ends in a restore operation (S9—S16). The store operation and the restore operation each comprise at least NO elementary downstream shift operations. The set of scan chains (C0, C1) includes a short chain (C1) and a detour chain (C0; C1), wherein the short chain (C1) has a length N1 shorter than NO, and the electronic device (10) comprises a buffer chain (B1) with a length of K = N0 - N1, which has an input end and an output end, which are opposite ends of the buffer chain (B1), with the output end of the short chain (C0) connected or connectable to the input end of the buffer chain (B1 ) and the output end of the buffer chain (B1) connected or connectable to the memory unit (MEM). The buffer chain (B1) is provided at least partly by the detour chain (C0; C1). A method of operating the electronic device (10) is also proposed.
摘要翻译：描述了包括一组两个或更多个扫描链（C0，C1）和存储单元（MEM）的电子设备（10）。每个扫描链（C0，C1）具有作为相应扫描链的相对端的输入端和输出端，并且每个扫描链（C0，C1，C2）包括一系列有状态元件（F3 ，F2，F1，F0），并且每个扫描链（C0，C1）被布置成保持具有与所述输入端和输出端的长度相同的长度的串（ABCDEFGH; IJKLMN）相应的扫描链（C0; C1），即与链的有状态元素的数量相同。扫描链（C0，C1）的串在存储操作（S1- S8）中经由相应的输出端从扫描链（C0，C1）并行移位到存储单元（MEM）中并从存储器返回单元（MEM）在恢复操作中通过相应的输入端进入相应的扫描链（C0，C1）（S9-S16）。存储操作和恢复操作每个至少包括没有基本的下游移位操作。扫描链（C0，C1）组包括短链（C1）和绕行链（C0; C1），其中短链（C1）具有比NO短的长度N1，电子装置（10）包括具有长度为K = N0-N1的缓冲链（B1），其具有作为缓冲链（B1）的相对端的输入端和输出端，短链（C0）的输出端连接或可连接到缓冲链（B1）的输入端和连接或连接到存储器单元（MEM）的缓冲链（B1）的输出端。缓冲链（B1）至少部分地由迂回链（C0; C1）提供。还提出了一种操作电子设备（10）的方法。

10. 发明申请

WO2014013298A1 REGISTER FILE MODULE AND METHOD THEREFOR 审中-公开
标题翻译：寄存器文件模块及其方法
公开(公告)号：WO2014013298A1
公开(公告)日：2014-01-23
申请号：PCT/IB2012/053721
申请日：2012-07-20
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , KUZMIN, Dan
发明人： PRIEL, Michael , FLESHEL, Leonid , KUZMIN, Dan
IPC分类号： G11C7/10 , G11C7/22 , G06F1/00
CPC分类号： G11C7/1072 , G11C7/065 , G11C7/1039 , G11C7/22 , G11C19/00 , G11C19/28 , G11C29/32 , G11C2207/007
摘要： A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit- cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.
摘要翻译：描述了包括至少一个包括多个锁存装置的寄存器阵列的寄存器文件模块。多个锁存装置被布置成当寄存器文件模块被配置为在第一功能操作模式下操作时，单独地提供存储位单元，并且至少一个时钟控制部件被布置成接收时钟信号并传播时钟信号到至少一个寄存器阵列内的锁存器件。寄存器文件模块可配置为以第二扫描模式操作，其中至少一个寄存器阵列内的锁存器件被布置成至少一个扫描链。所述至少一个时钟控制部件布置成将所述时钟信号传播到所述至少一个寄存器阵列内的锁存器件，使得所述至少一个扫描链内的另外的锁存器件接收所述时钟信号的反相形式。

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