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1. 发明申请

WO2012038882A9 STATISTICS COUNTERS STORED IN FAST AND SLOW MEMORIES 审中-公开
标题翻译：统计数据库存储在快速和缓慢的记忆
公开(公告)号：WO2012038882A9
公开(公告)日：2013-11-21
申请号：PCT/IB2011054101
申请日：2011-09-19
申请人： ERICSSON TELEFON AB L M , CHEN EDMUND G , ALLEYNE BRIAN , HATHAWAY ROBERT , ROZARIO RANJIT J , BASSO TODD
发明人： CHEN EDMUND G , ALLEYNE BRIAN , HATHAWAY ROBERT , ROZARIO RANJIT J , BASSO TODD
IPC分类号： H04L12/26 , H03K21/16 , H04L12/24
CPC分类号： H03K21/38 , H03K21/16
摘要： A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
摘要翻译：一种在存储器控制器中执行的方法，用于将分段计数器分为主存储器和次存储器，主存储器更快。发生需要增加分段计数器之一并且存储器控制器通过增加主存储器中的相应主要部分来进行响应的事件。每次主要部件在内存控制器上滚动时，都会确定要更新次要部件。此外，存储器控制器周期性地确定分段计数器的次要部分应该被机会性地更新。机会更新是基于概率函数和随机数。辅助部分至少包括不在主要部分中的分段计数器的所有位，并存储在辅助存储器中。每次发生对次要部件的更新时，分段计数器的辅助部件和主要部件都必须更新。

2. 发明申请

WO2013179089A1 SEQUENTIAL LOGIC CIRCUIT AND METHOD OF PROVIDING SETUP TIMING VIOLATION TOLERANCE THEREFOR 审中-公开
标题翻译：顺序逻辑电路及其提供设置时序违反的方法
公开(公告)号：WO2013179089A1
公开(公告)日：2013-12-05
申请号：PCT/IB2012/052700
申请日：2012-05-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
发明人： PRIEL, Michael , FLESHEL, Leonid , ROZEN, Anton
IPC分类号： H03K19/173 , H03K21/16
CPC分类号： H03K19/0016 , H03K5/135 , H03K19/00323 , H03K19/00369 , H03K19/173
摘要： A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby comprising a first logical state. The sequential logic circuit is arranged to operate in at least a first operating mode in which the data input of the first latch component and the data input of the second latch component are operably coupled to a first input of the sequential logic circuit, and in which the clock signals provided to the first and second latch components are such that a transition of the second latch component from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component from a transparent state to a latched state for a time period for receiving late data.
摘要翻译：一种顺序逻辑电路，包括：第一锁存器组件，包括布置成接收输入信号的数据输入;布置成输出第一锁存器组件的当前逻辑状态的数据输出和布置成接收时钟信号的时钟输入; 所述第一锁存部件被布置为在接收到的所述时钟信号时包括透明状态，由此包括第一逻辑状态，并且包括在接收到的所述时钟信号的锁存状态，由此包括第二逻辑状态，以及包括数据输入的第二锁存部件布置成接收输入信号，数据输出可操作地耦合到顺序逻辑电路的输出并且被布置成输出第二锁存部件的当前状态和布置成接收时钟信号的时钟输入; 所述第二锁存器组件被布置为在接收到的所述时钟信号后包括透明状态，由此包括第二逻辑状态，并且包括在接收到的所述时钟信号时的锁存状态，由此包括第一逻辑状态。顺序逻辑电路被布置为在至少第一操作模式中操作，其中第一锁存部件的数据输入和第二锁存部件的数据输入可操作地耦合到顺序逻辑电路的第一输入，并且其中提供给第一和第二锁存部件的时钟信号使得第二锁存部件从透明状态到锁存状态的转变相对于第一锁存部件从透明状态到锁存状态的对应转变而延迟，接收延迟数据的时间段。

3. 发明申请

WO2012038882A1 STATISTICS COUNTER STORED IN FAST AND SLOW MEMORIES 审中-公开
标题翻译：统计数据库存储在快速和慢速记忆中
公开(公告)号：WO2012038882A1
公开(公告)日：2012-03-29
申请号：PCT/IB2011/054101
申请日：2011-09-19
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , CHEN, Edmund G. , ALLEYNE, Brian , HATHAWAY, Robert , ROZARIO, Ranjit J. , BASSO, Todd
发明人： CHEN, Edmund G. , ALLEYNE, Brian , HATHAWAY, Robert , ROZARIO, Ranjit J. , BASSO, Todd
IPC分类号： H04L12/26 , H04L12/24 , H03K21/16
CPC分类号： H03K21/38 , H03K21/16
摘要： A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
摘要翻译：一种在存储器控制器中执行的方法，用于将分段计数器分为主存储器和次存储器，主存储器更快。发生需要增加分段计数器之一并且存储器控制器通过增加主存储器中的相应主要部分来进行响应的事件。每次主要部件在内存控制器上滚动时，都会确定要更新次要部件。此外，存储器控制器周期性地确定分段计数器的次要部分应该被机会性地更新。机会更新是基于概率函数和随机数。辅助部分至少包括不在主要部分中的分段计数器的所有位，并存储在辅助存储器中。每次发生对次要部件的更新时，分段计数器的辅助部件和主要部件都必须更新。

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