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1. 发明申请

WO2011082778A2 METHOD FOR PRODUCING AN ELECTRONIC UNIT AND ELECTRONIC UNIT 审中-公开
标题翻译：方法用于制造电子模块及电子组装
公开(公告)号：WO2011082778A2
公开(公告)日：2011-07-14
申请号：PCT/EP2010007628
申请日：2010-12-14
申请人： FRAUNHOFER GES FORSCHUNG , UNIV BERLIN TECH , OSTMANN ANDREAS , DIONYSIOS MANESSIS , BOETTCHER LARS , KARASZKIEWICZ STEFAN
发明人： OSTMANN ANDREAS , DIONYSIOS MANESSIS , BOETTCHER LARS , KARASZKIEWICZ STEFAN
IPC分类号： H01L21/60
CPC分类号： H05K1/188 , H01L21/4832 , H01L21/56 , H01L23/3107 , H01L24/16 , H01L24/24 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/82 , H01L24/83 , H01L2221/68377 , H01L2223/54426 , H01L2224/0401 , H01L2224/04105 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/136 , H01L2224/2402 , H01L2224/2919 , H01L2224/81121 , H01L2224/81801 , H01L2224/83192 , H01L2224/838 , H01L2224/92 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01046 , H01L2924/0105 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/0665 , H01L2924/07802 , H05K3/025 , H05K2201/0969 , H05K2201/09745 , H05K2203/0353 , H01L2224/81 , H01L2224/82 , H01L2224/83 , H01L2224/13099 , H01L2924/00 , H01L2924/014
摘要： The invention relates to a method for producing an electronic unit, wherein at least one electronic component is at least partially embedded in an insulating material, comprising the following steps: providing a film assembly with at least one conductive layer and a carrier layer, or with only a conductive layer, structuring the conductive layer such that openings in form of blind holes or through holes for receiving bumps are produced, which are connected to the contact surfaces of the at least one electronic component, applying an adhesive layer to the conductive layer provided with openings, placing the at least one component on the film assembly, or in the conductive layer, such that the bumps engage with the openings of the conductive layer, partially embedding the at least one component from the side opposite of the bumps (3) into a dielectric layer, removing the carrier layer of the film assembly, or a part of the conductive layer, such that the surface of the bumps is exposed, depositing a metallization layer on the side of the remaining conductive layer having the exposed bumps, and structuring the metallization layer and the conductive layer so as to produce conductor tracks that overlap with the bumps. The invention further relates to an electronic unit produced by such a method.
摘要翻译：本发明涉及一种用于制备电子组件，其中，至少一个电子部件被嵌入在绝缘材料至少部分地，具有以下步骤： - 仅一个导电提供膜结构或它具有至少一个导电层和一个载体层，或层， - 图案化该导电层，使得将要制造在盲孔或通，用于接收凸块的孔形式的开口，其被连接到至少一个电子部件的接触表面， - 所述有孔的导电层上施加粘合剂层， - 放置在所述薄膜结构或导电层，使得所述凸块接合导电层的开口在所述至少一个部件， - 在相反的一侧部分地嵌入所述凸块（3）的至少一种组分，所述 lektrikumsschicht， - 去除所述薄膜结构的支撑层或导电层的一部分，使得所述凸块的表面被暴露， - 沉积在剩余的导电层的一侧上的金属化层，以暴露的凸块， - 图案化该金属化层以及用于制造该导电层的与所述凸块重叠的导体轨迹。本发明还涉及到通过这样的方法，电子组件制备的溶液。

2. 发明申请

WO2007025753A3 MODULAR MICROELECTRONIC COMPONENT 审中-公开
标题翻译：模块化微电子元件
公开(公告)号：WO2007025753A3
公开(公告)日：2007-05-10
申请号：PCT/EP2006008520
申请日：2006-08-29
申请人： FRAUNHOFER GES FORSCHUNG , UNIV BERLIN TECH , NIEDERMAYER MICHAEL , OSTMANN ANDREAS , GUTTOWSKI STEPHAN , GRUNDMANN STEFAN , THOMASIUS ROLF , POLITYKO DMITRY-DAVID
发明人： NIEDERMAYER MICHAEL , OSTMANN ANDREAS , GUTTOWSKI STEPHAN , GRUNDMANN STEFAN , THOMASIUS ROLF , POLITYKO DMITRY-DAVID
IPC分类号： H05K1/14 , H05K3/36
CPC分类号： H05K1/144 , H05K3/284 , H05K3/366 , H05K3/368 , H05K3/403 , H05K2201/0919
摘要： The invention relates to a modular microelectronic component and a method for the production thereof. The inventive method comprises the following steps: a) at least two functional layers (12, 22) are produced, each of which is provided with a planar support (10, 20), electronic components, 1 to 5, 8, 9) located on the support (10, 20), a conductor structure, and electrical first contact points (11, 21) located on the edge (6, 23) of the support (10, 20). The conductor structure contacts the electronic components at least in part while being at least partly connected to the first contact points (11, 21) on the edge (6, 23) of the support (10, 20); b) the functional layers (12, 22) are placed on top of each other layer by layer; c) the functional layers (12, 22) are electrically connected via the first contact points (11, 21). The invention makes it possible to produce an extremely compact and robust microelectronic component while the adjusting effort can be kept very low compared to other modular methods when designing the individual functional layers. Very different aspect ratios of the individual functional layers are rather unproblematic during system integration, resulting in a small amount of development effort.
摘要翻译：本发明涉及一种模块化微电子元件及其制备方法。根据本发明，该方法包括以下步骤：a）制备至少两个功能层（12，22），其中，每个功能层（12，22）包括所述载体（10上的扁平支承件（10，20），20）设置的电子元件（1 -5，8,9），导体在边缘处利用Dende电第一接触点的载体（10，20）（11,21），其中，所述导体图案中，电子部件至少部分地由与接触并至少部分的结构和（6，23）在载体（10，20）连接的边缘（6，23）的第一接触点（11，21）; b）该研磨功能该ionsschichten的层（12，22）; C）电连接经由第一接触点（11，21）的功能层（12，22）。本发明使得有可能生产一种非常紧凑和坚固的微电子元件。在这种情况下，表决sauf可以在从其他模块化方法的各个功能层的设计中保持非常低的墙。非常各个功能层的不同的纵横比使相当容易，从而导致较低的开发努力允许系统集成。

3. 发明申请

WO0137338A3 METHOD FOR INTEGRATING A CHIP IN A PRINTED BOARD AND INTEGRATED CIRCUIT 审中-公开
标题翻译：方法整合电路板和集成电路芯片的
公开(公告)号：WO0137338A3
公开(公告)日：2001-12-27
申请号：PCT/EP0011380
申请日：2000-11-16
申请人： FRAUNHOFER GES FORSCHUNG , JUNG ERIK , OSTMANN ANDREAS , LANDESBERGER CHRISTOPH
发明人： JUNG ERIK , OSTMANN ANDREAS , LANDESBERGER CHRISTOPH
IPC分类号： H01L21/60 , H01L23/52 , H01L23/538 , H05K1/18 , H01L23/498 , H01L21/98
CPC分类号： H01L23/5389 , H01L23/538 , H01L24/24 , H01L24/82 , H01L2224/24051 , H01L2224/24225 , H01L2224/24226 , H01L2224/73267 , H01L2224/82039 , H01L2224/92244 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01061 , H01L2924/01068 , H01L2924/14 , H01L2924/19043 , H05K1/185
摘要： The invention relates to a method for generating a highly integrated structure. To this end, a chip is embedded in a printed board by thinning the back of said chip, applying it to a base layer of the printed board and covering it by another printed board layer. Recesses are produced in said printed board layer that extend up to a conductor structure of the base layer of the printed board and to connection surfaces of the chip. Contact is established via a contact conductor structure (10) that extends to the connection surface (3) of the chip and the conductor structure (6) of the base layer of the printed board. This method is repeated layer by layer to give multilayer three-dimensional structures.
摘要翻译：为了产生一个高度集成的结构，芯片被嵌入由芯片的印刷电路板内变薄背面，被施加到印刷电路板底层，由另一印刷电路板底部层包围，在凹部，其延伸至印刷电路板的底层和Anschssluflächen的导体图案中产生芯片延伸。的接触是通过向上延伸到芯片和（6）所述电路板的底部层延伸的导体图案的连接表面（3）Kontaktierungsleiterstruktur（10）制成。对于多层的三维结构，该过程由层重复层。

4. 发明申请

WO2010086111A3 METHOD FOR GENERATING METAL CRYSTALLINE SURFACE STRUCTURES IN THE COURSE OF GALVANIC METAL DEPOSITION 审中-公开
标题翻译：用金属分离法生产金属晶体表面结构的方法
公开(公告)号：WO2010086111A3
公开(公告)日：2010-10-07
申请号：PCT/EP2010000331
申请日：2010-01-20
申请人： FRAUNHOFER GES FORSCHUNG , SCHMIDT RALF , ZWANZIG MICHAEL , FIEDLER STEFAN , OSTMANN ANDREAS , ASCHENBRENNER ROLF
发明人： SCHMIDT RALF , ZWANZIG MICHAEL , FIEDLER STEFAN , OSTMANN ANDREAS , ASCHENBRENNER ROLF
IPC分类号： C25D7/06 , C25D17/00
CPC分类号： C25D7/00 , C25D5/00 , C25D5/006 , C25D17/001
摘要： The invention relates to a method for generating metal crystalline surface structures in the course of a galvanic metal deposition on an electrode surface disposed within an electrolyte fluid relative to a counter-electrode comprising the metal to be deposited. The invention is characterized in that the electrode surface and a surface that can be associated with the counter-electrode are disposed such that the electrode and counter-electrode surface are at rest relative to the electrolyte fluid, and that an electrical voltage is applied between the electrode and counter-electrode surface, wherein a layer forms within the electrolyte fluid adjacent to the electrode surface and having a layer thickness extending orthogonally to the electrode surface, within which a concentration gradient determined by the metal ions and oriented orthogonally to the electrode surface, and a density gradient resulting therefrom, are initiated.
摘要翻译：公开了一种用于通过在电极表面上电镀的金属沉积，其中包含对置电极被定位成抵靠金属的电解质流体中待沉积的手段制备金属结晶表面结构的方法。本发明的特征在于，在电极表面和对电极可归因表面水平设置，使得在相对于所述电解质流体其余部分的电极和反电极的表面，并且所述电极和反电极的表面之间的电施加电压时，在该相邻的具有正交ersteckenden到电极表面层厚度到电极表面，在其内是一对流形成其由一个条件中的金属离子的仅启动和正交地定向到电极表面的浓度梯度，所得到的密度梯度形成电解流体内的层。

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