专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2006078744A2 METHOD AND SYSTEM FOR MANAGING A SUSPEND REQUEST IN A FLASH MEMORY 审中-公开
标题翻译：用于管理闪存中的暂停请求的方法和系统
公开(公告)号：WO2006078744A2
公开(公告)日：2006-07-27
申请号：PCT/US2006/001776
申请日：2006-01-19
申请人： ATMEL CORPORATION , SURICO, Stefano , BARTOLI, Simone , MARZIANI, Monica , FIGINI, Luca
发明人： SURICO, Stefano , BARTOLI, Simone , MARZIANI, Monica , FIGINI, Luca
IPC分类号： G06F12/00
CPC分类号： G06F9/30003 , G11C2216/22
摘要： System and method for the managing of suspend requests in flash memory devices. The system includes a microcontroller performing a modify operation on a flash memory array, a memory coupled to the microcontroller and storing suspend sequence code for causing a suspension of the modify operation when executed by the microcontroller, and suspend circuitry that receives a suspend request from a user to suspend the modify operation and starts the execution of the suspend sequence code.
摘要翻译：用于管理闪存设备中的挂起请求的系统和方法。该系统包括微控制器，其对闪速存储器阵列进行修改操作，耦合到微控制器的存储器，并且存储暂停序列代码，用于当由微控制器执行时导致暂停修改操作;以及暂停从微控制器接收暂停请求的电路用户暂停修改操作并开始执行挂起序列代码。

2. 发明申请

WO2006041730A2 METHOD AND SYSTEM FOR A PROGRAMMING APPROACH FOR A NONVOLATILE ELECTRONIC DEVICE 审中-公开
标题翻译：用于非线性电子器件的编程方法的方法和系统
公开(公告)号：WO2006041730A2
公开(公告)日：2006-04-20
申请号：PCT/US2005/035296
申请日：2005-09-30
申请人： ATMEL CORPORATION , SURICO, Stefano , BARTOLI, Simone , TASSAN CASER, Fabio , MARZIANI, Monica
发明人： SURICO, Stefano , BARTOLI, Simone , TASSAN CASER, Fabio , MARZIANI, Monica
IPC分类号： G11C16/06
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/12 , G11C16/3454 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括使用初始类型的参考电压值执行编程算法的初始验证步骤，以及使用第二类型的参考电压值来执行编程算法中的一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中为理想分布的单元确保期望的编程。

3. 发明申请

WO2008124094A1 APPARATUS AND METHOD TO TEST NON-VOLATILE MEMORY 审中-公开
标题翻译：测试非易失性存储器的装置和方法
公开(公告)号：WO2008124094A1
公开(公告)日：2008-10-16
申请号：PCT/US2008/004446
申请日：2008-04-04
申请人： ATMEL CORPORATION , SURICO, Stefano , SIVERO, Stefano , BARTOLI, Simone , PASSERINI, Marco
发明人： SURICO, Stefano , SIVERO, Stefano , BARTOLI, Simone , PASSERINI, Marco
IPC分类号： G06F11/00
CPC分类号： G11C16/10
摘要： Some embodiments disclosed comprise apparatus and methods relating to a nonvolatile memory comprising an input output buffer; a latch circuit coupled to the input/output buffers; a memory array having nonvolatile memory cells coupled to an input/output buffer; a command user interface coupled to the input/output buffer and the latch circuit; a microcontroller coupled to the command user interface; a read-only memory storing instructions to be executed by the microcontroller; and a switch-instruction circuitry coupled to the latch circuit, the read-only memory and the digital control circuitry to selectively provide instructions to the microcontroller from the read-only memory and to selectively provide substitute instructions under control of the command user interface, the substitute instructions received at the input/output buffer from an external source. Other embodiments and methods are disclosed.
摘要翻译：公开的一些实施例包括涉及包括输入输出缓冲器的非易失性存储器的装置和方法; 耦合到输入/输出缓冲器的锁存电路; 具有耦合到输入/输出缓冲器的非易失性存储单元的存储器阵列; 耦合到输入/输出缓冲器和锁存电路的命令用户界面; 耦合到命令用户界面的微控制器; 存储由微控制器执行的指令的只读存储器; 以及耦合到所述锁存电路，所述只读存储器和所述数字控制电路的开关指令电路，用于从所述只读存储器选择性地向所述微控制器提供指令，并且在所述命令用户界面的控制下选择性地提供替代指令，从外部源代替在输入/输出缓冲器处接收的指令。公开了其他实施例和方法。

4. 发明申请

WO2006044190A2 METHOD AND SYSTEM FOR MANAGING ADDRESS BITS DURING BUFFERED PROGRAM OPERATIONS IN A MEMORY DEVICE 审中-公开
标题翻译：在存储器件中缓存程序运行期间管理地址位的方法和系统
公开(公告)号：WO2006044190A2
公开(公告)日：2006-04-27
申请号：PCT/US2005/035658
申请日：2005-10-04
申请人： ATMEL CORPORATION , BARTOLI, Simone , SURICO, Stefano , MANFRE, Davide , FERRARIO, Donato
发明人： BARTOLI, Simone , SURICO, Stefano , MANFRE, Davide , FERRARIO, Donato
IPC分类号： G06F12/10
CPC分类号： G06F12/04 , G11C16/10 , G11C2216/14
摘要： A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations. The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words. A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words.
摘要翻译：描述用于管理用于多个单词的缓冲程序操作的方法和系统。一方面，该方法和系统包括提供包括多个位置的多个位置和至少一个位置的内部缓冲器。每个词都存储在多个位置的位置。这些单词与位置的内部地址位相关联。至少一个内部地址位是与所有字对应的至少一个组地址位。内部地址位的剩余部分与至少一个字相关联。所述至少一个位位置存储所述字的至少一个组地址位。因此，在一个方面，该方法和系统包括存储缓冲器位置之一中的每一个字。该方法和系统还包括将至少一个组地址位与每个字的缓冲器位置相关联。

5. 发明申请

WO2008076553A2 A NEW IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM 审中-公开
标题翻译：具有高写并发性的闪存存储器的冗余冗余的新实现
公开(公告)号：WO2008076553A2
公开(公告)日：2008-06-26
申请号：PCT/US2007/084460
申请日：2007-11-12
申请人： ATMEL CORPORATION , BARTOLI, Simone , SURICO, Stefano , SACCO, Andrea , MOSTOLA, Maria
发明人： BARTOLI, Simone , SURICO, Stefano , SACCO, Andrea , MOSTOLA, Maria
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array (300) has r columns of redundant memory cells (306), r redundant senses (312), and a redundant column decoder (308). Redundant address registers (332) store addresses of defective regular memory cells. Redundant latches (338) are provided in n groups of r latches. Redundancy comparison logic (330) compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal (333) to disable the regular senses (310) for one of the n groups of m columns, an ENABLE_LATCH signal (334) to one of the n groups of m columns to disable corresponding regular senses, and one of r REDO signals (336) to a respective one of the r redundant latches (338) in one of the n groups that is disabled. The selected one of the redundant latches (338) activates one of the r redundant senses (312) to access a redundant column.
摘要翻译：冗余存储器阵列（300）具有r列的冗余存储器单元（306），r冗余感测（312）和冗余列解码器（308）。冗余地址寄存器（332）存储有缺陷的常规存储单元的地址。冗余锁存器（338）设置在n组r个锁存器中。冗余比较逻辑（330）将缺陷规则存储器单元的地址与外部输入地址进行比较。如果比较是真实的，则提供的是：禁用n列m列中的一个的常规感测（310）的DISABLE_LOAD信号（333），到m列的n组之一的ENABLE_LATCH信号（334）禁用相应的常规感测，并且将r个REDO信号中的一个（336）禁止到被禁用的n个组中的一个中的r个冗余锁存器（338）中的相应一个。所选择的冗余锁存器（338）中的一个激活r个冗余感测（312）中的一个以访问冗余列。

6. 发明申请

WO2006119404A2 METHOD AND SYSTEM FOR CONFIGURING PARAMETERS FOR A FLASH MEMORY 审中-公开
标题翻译：用于配置闪速存储器参数的方法和系统
公开(公告)号：WO2006119404A2
公开(公告)日：2006-11-09
申请号：PCT/US2006/017096
申请日：2006-05-03
申请人： ATMEL CORPORATION , SURICO, Stefano , BARTOLI, Simone , MARSELLA, Mirella , BOSISIO, Giorgio
发明人： SURICO, Stefano , BARTOLI, Simone , MARSELLA, Mirella , BOSISIO, Giorgio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： Method and system for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a read-only memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation. In another aspect, one or more selected configuration values not stored in a ROM are changed if a tested flash memory operation is not within desired specifications.
摘要翻译：用于配置闪存设备中使用的参数的方法和系统。从只读存储器检索加载指令和相关联的地址，并且该地址用于选择存储配置值的配置寄存器。配置值加载到相关联的专用寄存器，以在闪存操作中配置闪存的参数。在另一方面，如果测试的闪速存储器操作不在期望的规范内，则不存储在ROM中的一个或多个选择的配置值被改变。

7. 发明申请

WO2006033832A2 NEW COMPENSATED METHOD TO IMPLEMENT A HIGH VOLTAGE DISCHARGE PHASE AFTER ERASE PULSE IN A FLASH MEMORY DEVICE 审中-公开
标题翻译：用于在闪存存储器件中擦除脉冲之后实现高电压放电相位的新补偿方法
公开(公告)号：WO2006033832A2
公开(公告)日：2006-03-30
申请号：PCT/US2005/031830
申请日：2005-09-07
申请人： ATMEL CORPORATION , BEDARIDA, Lorenzo , BARTOLI, Simone , ODDONE, Giorgio , MANFRÉ, Davide
发明人： BEDARIDA, Lorenzo , BARTOLI, Simone , ODDONE, Giorgio , MANFRÉ, Davide
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/12 , G11C16/10 , G11C16/22
摘要： A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
摘要翻译：一种闪速存储装置中的放电方法包括：在擦除操作之后启动存储单元的放电; 将第一放电电路耦合到栅极 - 体积电容器的第一板，以及将第二放电电路耦合到栅极 - 体积电容器的第二板，其中第一板表示存储单元的公共栅极节点，第二板表示存储单元的批量源节点; 并将公共栅极节点和体源节点耦合到地以提供完全放电。注入第一板的电流大约等于从第二板提取的电流。以这种方式，在没有复杂设计或限压器的情况下，栅极和体源电压的危险振荡消除，而不会在擦除操作之后不牺牲快速放电。因此，放电操作的可靠性显着提高。

8. 发明申请

WO2008115570A1 NAN FLASH MEMORY WITH HIERARCHICAL BITLINE AND WORDLINE ARCHITECTURE 审中-公开
标题翻译：具有分层位线和WORDLINE架构的NAN FLASH存储器
公开(公告)号：WO2008115570A1
公开(公告)日：2008-09-25
申请号：PCT/US2008/003716
申请日：2008-03-20
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , BEDARIDA, Lorenzo , BARTOLI, Simone , TASSAN CASER, Fabio
发明人： FRULIO, Massimiliano , BEDARIDA, Lorenzo , BARTOLI, Simone , TASSAN CASER, Fabio
IPC分类号： G11C16/04 , G11C16/08
CPC分类号： G11C16/08 , G11C5/025 , G11C5/063
摘要： Some embodiments of the apparatus relate to NAND-like memory arrays employing high- density NOR-like memory devices. A flash memory integrated circuit includes a plurality of flash memory arrays. A global wordline driver is associated with each array, each global wordline driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bitlines. A plurality of sub-arrays in each array each include a plurality of NAND flash memory cells coupled to local wordlines and local bitlines. A local wordline driver is associated with each sub-array and coupled to the plurality of select lines and configured to drive ones of the local wordlines in its sub-array associated with selected ones of the plurality of NAND flash memory cells in its sub-array. A local bitline driver is coupled between selected ones of the local bitlines in each sub-array and selected ones of the plurality of bitlines.
摘要翻译：该装置的一些实施例涉及采用高密度NOR样存储器件的类NAND存储器阵列。闪存集成电路包括多个闪存阵列。全局字线驱动器与每个阵列相关联，每个全局字线驱动器耦合到多个选择线。多个读出放大器分别耦合到多个位线。每个阵列中的多个子阵列各自包括耦合到本地字线和本地位线的多个NAND快闪存储器单元。本地字线驱动器与每个子阵列相关联并且耦合到多个选择线并且被配置为驱动与其子阵列中的多个NAND快闪存储器单元中的选定的一个相关联的其子阵列中的本地字线中的一个。局部位线驱动器耦合在每个子阵列中的本地位线的选定的位线和多个位线中的选定的位线之间。

9. 发明申请

WO2006041790A2 COLUMN DECODING ARCHITECTURE FOR FLASH MEMORIES 审中-公开
标题翻译：闪存记忆体解码架构
公开(公告)号：WO2006041790A2
公开(公告)日：2006-04-20
申请号：PCT/US2005/035528
申请日：2005-09-30
申请人： ATMEL CORPORATION , SIVERO, Stefano , BARTOLI, Simone , TASSAN CASER, Fabio , RIVA, REGGIORI, Riccardo
发明人： SIVERO, Stefano , BARTOLI, Simone , TASSAN CASER, Fabio , RIVA, REGGIORI, Riccardo
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/1021 , G11C16/24
摘要： An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.
摘要翻译：用于闪存器件的列解码的改进方法和设备利用长度大于逻辑页长度的突发页。当发生初始地址的错位时，跨逻辑页面边界的有效读取是可能的。只有当读取跨越突发页面边界时，存储器件才进入等待状态。这使存储器件进入等待状态的时间量最小化。在优选实施例中，这通过对馈送三电平解码级列解码器的第三电平的控制信号的不同管理来实现。不需要对架构或列解码器选择器的数量进行更改。因此，同步读取期间的存储器访问时间得到改善。

10. 发明申请

WO2008089160A2 SENSE ARCHITECTURE 审中-公开
标题翻译：感应体系结构
公开(公告)号：WO2008089160A2
公开(公告)日：2008-07-24
申请号：PCT/US2008/051026
申请日：2008-01-15
申请人： ATMEL CORPORATION , PELLI, Gabriele , BEDARIDA, Lorenzo , BARTOLI, Simone , BOSISIO, Giorgio
发明人： PELLI, Gabriele , BEDARIDA, Lorenzo , BARTOLI, Simone , BOSISIO, Giorgio
IPC分类号： G11C16/28
CPC分类号： G11C16/28
摘要： A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.
摘要翻译：公开了一种存储系统。在一个实施例中，存储器系统包括第一位线，其中第一位线产生第一瞬态电流。存储器系统还包括耦合到第一位线的读出放大器。存储器系统还包括耦合到读出放大器的第二位线，其中第二位线产生等于第一瞬态电流的第二瞬态电流。读出放大器能够消除第一和第二瞬态电流。根据本文公开的系统，可以确定存储器单元的状态而不受瞬态电流的不利影响。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式