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    • 2. 发明申请
    • METHOD OF FORMING P-N JUNCTION IN SOLAR CELL SUBSTRATE
    • 在太阳能电池基板中形成P-N结的方法
    • WO2012145060A1
    • 2012-10-26
    • PCT/US2012/025082
    • 2012-02-14
    • APPLIED MATERIALS, INC.KUMAR, PrabhatDOMINGUEZ, JasonTANNER, David
    • KUMAR, PrabhatDOMINGUEZ, JasonTANNER, David
    • H01L31/06H01L31/042H01L31/18
    • H01L31/02363H01L31/068H01L31/1804Y02E10/547Y02P70/521
    • Embodiments of the present invention relate to a single step diffusion process used in selective emitter solar cell fabrication. In one embodiment, a dopant paste is selectively applied on a front surface of a substrate having opposite conductivity type from the dopant paste. The substrate is then exposed to a dopant containing vapor to deposit a doping layer having opposite conductivity type from the substrate on the front surface of the substrate. While the substrate is exposed to the dopant containing vapor, a portion of the dopant paste also contribute to deposition of the doping layer via gas phase transport of doping atoms from the dopant paste. The substrate is then heated in an atmosphere comprising oxygen and/or nitrogen to a temperature sufficient to cause the dopant atoms in the dopant paste and the doping layer to diffuse into the substrate, forming heavily and lightly doped emitter regions.
    • 本发明的实施例涉及用于选择性发射极太阳能电池制造的单步骤扩散方法。 在一个实施例中,掺杂剂浆料选择性地施加在与掺杂剂浆料相反的导电类型的衬底的前表面上。 然后将衬底暴露于含有蒸汽的掺杂剂以从衬底的前表面上的衬底沉积具有相反导电类型的掺杂层。 当衬底暴露于含有掺杂剂的蒸汽的掺杂剂时,掺杂剂浆料的一部分也有助于通过掺杂原子从掺杂剂浆料的气相转移来沉积掺杂层。 然后将衬底在包括氧和/或氮的气氛中加热到足以使掺杂剂浆料中的掺杂剂原子和掺杂层扩散到衬底中的温度,形成重度和轻掺杂的发射极区域。
    • 6. 发明申请
    • DICING TAPE THERMAL MANAGEMENT BY WAFER FRAME SUPPORT RING COOLING DURING PLASMA DICING
    • 通过水平框架支撑滚筒冷却的等温线热管理
    • WO2015175267A1
    • 2015-11-19
    • PCT/US2015/029259
    • 2015-05-05
    • APPLIED MATERIALS, INC.
    • LEI, Wei-ShengKUMAR, PrabhatEATON, BradKUMAR, Ajay
    • H01L21/301H01L21/78
    • H01L21/82H01L21/3065H01L21/67H01L21/67069H01L21/67092H01L21/67109H01L21/67207H01L21/78
    • Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves introducing a substrate supported by a substrate carrier into a plasma etch chamber. The substrate has a patterned mask thereon covering integrated circuits and exposing streets of the substrate. The substrate carrier has a backside. The method also involves supporting at least a portion of the backside of the substrate carrier on a chuck of the plasma etch chamber. The method also involves cooling substantially all of the backside of the substrate carrier, the cooling involving cooling at least a first portion of the backside of the substrate carrier by the chuck. The method also involves plasma etching the substrate through the streets to singulate the integrated circuits while performing the cooling substantially all of the backside of the substrate carrier.
    • 对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。 在一个实例中,对具有多个集成电路的半导体晶片进行切割的方法包括将由衬底载体支撑的衬底引入等离子体蚀刻室。 衬底上具有图案化掩模,覆盖集成电路并暴露衬底的街道。 衬底载体具有背面。 该方法还涉及将衬底载体的背侧的至少一部分支撑在等离子体蚀刻室的卡盘上。 该方法还包括冷却基板载体的基本上所有背面,冷却涉及通过卡盘冷却基板载体的背面的至少第一部分。 该方法还涉及通过街道等离子体蚀刻衬底以对集成电路进行单片化,同时基本上全部衬底载体的背面进行冷却。
    • 7. 发明申请
    • RESIDUE REMOVAL FROM SINGULATED DIE SIDEWALL
    • 从平整的DIE小屋中移除残留物
    • WO2015153592A1
    • 2015-10-08
    • PCT/US2015/023564
    • 2015-03-31
    • APPLIED MATERIALS, INC.
    • LEI, Wei-ShengKUMAR, PrabhatPAPANU, James S.KUMAR, AjayEATON, Brad
    • H01L21/301H01L21/76H01L21/78
    • H01L21/02076H01L21/67092H01L21/67207
    • Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the mask to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing etch residue from sidewalls of the singulated integrated circuits.
    • 对半导体晶片的切割方法,具有多个集成电路的各晶片进行说明。 在一个示例中,对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模,该掩模包括覆盖并保护集成电路的层。 该方法还包括用激光划线工艺对掩模进行图案化以在掩模中提供间隙,在半导体晶片的间隙暴露集成电路之间的半导体晶片。 该方法还包括通过掩模中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。 该方法还涉及在等离子体蚀刻半导体晶片之后,从单个集成电路的侧壁去除蚀刻残留物。
    • 8. 发明申请
    • MONOLOTHIC MODULE ASSEMBLY FOR STANDARD CRYSTALLINE SILICON SOLAR CELLS
    • 标准晶体硅太阳能电池单体组件
    • WO2013062734A1
    • 2013-05-02
    • PCT/US2012/059011
    • 2012-10-05
    • APPLIED MATERIALS, INC.KUMAR, PrabhatPAAK, SunhomGEE, James M.
    • KUMAR, PrabhatPAAK, SunhomGEE, James M.
    • H01L31/05
    • H01L31/0504H01L31/0512Y02E10/50
    • Apparatuses and assembly methods are provided for a monolithic solar cell panel assembly. The assembly comprises an array of solar cells having front electrical contacts and back electrical contacts, wherein a first set of the solar cells in the array are aligned to be electrically connected in series through a back circuit sheet having an array of back metal contacts connected to corresponding back electrical contacts on the first set of solar cells, and through a front circuit sheet having an array of front metal contacts connected to corresponding front electrical contacts on the first set of solar cells. Electrical connections may be made in a lamination step, in which an encapsulant polymer flows into gaps and an interconnect material connects the circuits to form the monolithic solar cell panel assembly.
    • 为单片太阳能电池板组件提供了装置和装配方法。 组件包括具有前电触头和背电触头的太阳能电池阵列,其中阵列中的第一组太阳能电池被对准以通过背电路片串联电连接,所述背板具有连接到 在第一组太阳能电池上的相应的后部电触点,以及通过连接到第一组太阳能电池组上的对应的前部电触点的前部金属触点阵列的前部电路板。 电连接可以在层压步骤中进行,其中密封剂聚合物流入间隙,并且互连材料连接电路以形成单片太阳能电池面板组件。