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1. 发明申请

WO2016081313A1 A METHOD OF MANUFACTURING HIGH RESISTIVITY SEMICONDUCTOR-ON-INSULATOR WAFERS WITH CHARGE TRAPPING LAYERS 审中-公开
标题翻译：制造具有电荷捕获层的高电阻半导体绝缘体波导的方法
公开(公告)号：WO2016081313A1
公开(公告)日：2016-05-26
申请号：PCT/US2015/060674
申请日：2015-11-13
申请人： SUNEDISON SEMICONDUCTOR LIMITED , PEIDOUS, Igor
发明人： PEIDOUS, Igor , LIBBERT, Jeffrey Louis , KOMMU, Srikanth , JONES, Andrew M. , PRATT, Samuel Christopher , MENDEZ, Horacio Josue , STANTON, Leslie George , DICKINSON, Michelle Rene
IPC分类号： H01L21/762
CPC分类号： H01L21/76251 , H01L21/02164 , H01L21/02238 , H01L21/02255 , H01L21/02529 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/76254
摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
摘要翻译：提供了在制造绝缘体上半导体器件时制备单晶半导体处理晶片的方法。准备单晶半导体处理晶片包括电荷捕获层，其被氧化。得到的绝缘体上半导体器件中的掩埋氧化物层包括电荷俘获层的氧化部分和单晶半导体器件层的氧化部分。

2. 发明申请

WO2007019002A2 METHODS FOR FABRICATING A STRESSED MOS DEVICE 审中-公开
标题翻译：用于制造受压MOS器件的方法
公开(公告)号：WO2007019002A2
公开(公告)日：2007-02-15
申请号：PCT/US2006/028197
申请日：2006-07-20
申请人： ADVANCED MICRO DEVICES, INC. , PEIDOUS, Igor , PELELLA, Mario, M.
发明人： PEIDOUS, Igor , PELELLA, Mario, M.
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A method for fabricating a stressed MOS device [30] in and on a semiconductor substrate [36] is provided. The method comprises the steps of forming a gate electrode [66] overlying the semiconductor substrate [36] and etching a first trench [82] and a second trench [84] in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode [66]. A stress inducing material [90] is selectively grown in the first trench [82] and in the second trench [84] and conductivity determining impurity ions are implanted into the stress inducing material [90] to form a source region [92] in the First trench [82] and a drain region [94] in the second trench [84]. To preserve the stress induced in the substrate, a layer of mechanically hard material [96] is deposited on the stress inducing material [90] after the step of ion implanting.
摘要翻译：提供了一种用于在半导体衬底[36]中和之上制造应力MOS器件[30]的方法。该方法包括以下步骤：在半导体衬底上形成覆盖半导体衬底[36]并蚀刻第一沟槽[82]和第二沟槽[84]的栅电极，第一沟槽和第二沟槽形成为对准与栅电极[66]。在第一沟槽[82]和第二沟槽[84]中选择性地生长应力诱导材料[90]，并且将导电性确定杂质离子注入到应力诱导材料[90]中以形成源极区域[92] 在第二沟槽[84]中的第一沟槽[82]和漏极区域[94]。为了保持在衬底中引起的应力，在离子注入步骤之后，将一层机械硬质材料沉积在应力诱导材料[90]上。

3. 发明申请

WO2017142704A1 HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED ON A SUBSTRATE WITH A ROUGH SURFACE 审中-公开
标题翻译：包含在具有粗糙表面的衬底上形成的电荷陷阱层的高电阻率绝缘体上硅衬底
公开(公告)号：WO2017142704A1
公开(公告)日：2017-08-24
申请号：PCT/US2017/015813
申请日：2017-01-31
申请人： SUNEDISON SEMICONDUCTOR LIMITED , PEIDOUS, Igor
发明人： PEIDOUS, Igor , JONES, Andrew M. , KOMMU, Srikanth , WANG, Gang , LIBBERT, Jeffrey L.
IPC分类号： H01L21/762 , H01L21/28
CPC分类号： H01L21/76254
摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.
摘要翻译：提供了多层复合结构和制备多层复合结构的方法。多层复合结构包括具有至少约500ohm-cm的最小体区电阻率的半导体处理衬底，并且单晶半导体处理衬底的前表面具有根据根部测量的至少约0.1微米的表面粗糙度均方法在至少30微米×30微米的表面积上。所述复合结构还包括与所述前表面接触的电荷俘获层，所述电荷俘获层包含多晶硅，所述多晶硅包含具有多个晶体取向的晶粒; 与电荷俘获层接触的介电层; 以及与介电层接触的单晶半导体器件层。

4. 发明申请

WO2013016341A2 METHODS OF FORMING A METAL SILICIDE REGION IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路中形成金属硅化物区域的方法
公开(公告)号：WO2013016341A2
公开(公告)日：2013-01-31
申请号：PCT/US2012/047986
申请日：2012-07-24
申请人： APPLIED MATERIALS, INC. , WARD, Michael G. , PEIDOUS, Igor V.
发明人： WARD, Michael G. , PEIDOUS, Igor V.
IPC分类号： H01L21/24 , H01L21/324
CPC分类号： H01L21/28518
摘要： Methods of forming a metal silicide region in an integrated circuit are provided herein. In some embodiments, a method of forming a metal silicide region in an integrated circuit includes forming a silicide-resistive region in a first region of a substrate, the substrate having the first region and a second region, wherein a mask layer is deposited atop the substrate and patterned to expose the first region; removing the mask layer after the silicide-resistive region is formed in the first region of the substrate; depositing a metal-containing layer on a first surface of the first region and a second surface of the second region; and annealing the deposited metal-containing layer to form a first metal silicide region in the second region.
摘要翻译：本文提供了在集成电路中形成金属硅化物区域的方法。在一些实施例中，一种在集成电路中形成金属硅化物区域的方法包括在衬底的第一区域中形成硅化物 - 电阻区域，所述衬底具有第一区域和第二区域，其中掩模层沉积在衬底并被图案化以暴露第一区域; 在衬底的第一区域中形成硅化物 - 电阻区之后，去除掩模层; 在第一区域的第一表面和第二区域的第二表面上沉积含金属层; 以及对沉积的含金属层进行退火以在第二区域中形成第一金属硅化物区域。

5. 发明申请

WO2008063543A2 STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION 审中-公开
标题翻译：应力增强型MOS晶体管及其制造方法
公开(公告)号：WO2008063543A2
公开(公告)日：2008-05-29
申请号：PCT/US2007024034
申请日：2007-11-16
申请人： ADVANCED MICRO DEVICES INC , PAL ROHIT , PEIDOUS IGOR , BROWN DAVID
发明人： PAL ROHIT , PEIDOUS IGOR , BROWN DAVID
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02639 , H01L21/823807 , H01L21/823814 , H01L29/045 , H01L29/165 , H01L29/66636
摘要： A stress enhanced MOS transistor [30] and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode [62] overlying and defining a channel region [68] in a monocrystalline semiconductor substrate [38]. A trench [72, 74] having a side surface [78, 80] facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material [82, 90] having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material [88, 100] having a second concentration of the substitutional atom. The second monocrystalline semiconductor material [82, 90] is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region [68] than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.
摘要翻译：提供了应力增强MOS晶体管[30]及其制造方法。在一个实施例中，该方法包括在单晶半导体衬底[38]中形成覆盖并限定沟道区[68]的栅电极[62]。具有面向沟道区的侧表面[78,80]的沟槽[72,74]蚀刻到与沟道区相邻的单晶半导体衬底中。沟槽填充有具有第一浓度的置换原子的第二单晶半导体材料[82,90]和具有第二浓度的置换原子的第三单晶半导体材料[88,100]。第二单晶半导体材料[82,90]被外延生长以具有足以在沟道区上施加更大应力的沿着侧表面的壁厚，而不是由具有第二单晶半导体材料的单晶半导体材料施加的应力如果沟槽仅由第三单晶材料填充，则为浓度。

6. 发明申请

WO2007019002A3 METHODS FOR FABRICATING A STRESSED MOS DEVICE 审中-公开
标题翻译：制造应力MOS器件的方法
公开(公告)号：WO2007019002A3
公开(公告)日：2007-03-29
申请号：PCT/US2006028197
申请日：2006-07-20
申请人： ADVANCED MICRO DEVICES INC , PEIDOUS IGOR , PELELLA MARIO M
发明人： PEIDOUS IGOR , PELELLA MARIO M
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A method for fabricating a stressed MOS device [30] in and on a semiconductor substrate [36] is provided. The method comprises the steps of forming a gate electrode [66] overlying the semiconductor substrate [36] and etching a first trench [82] and a second trench [84] in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode [66]. A stress inducing material [90] is selectively grown in the first trench [82] and in the second trench [84] and conductivity determining impurity ions are implanted into the stress inducing material [90] to form a source region [92] in the First trench [82] and a drain region [94] in the second trench [84]. To preserve the stress induced in the substrate, a layer of mechanically hard material [96] is deposited on the stress inducing material [90] after the step of ion implanting.
摘要翻译：提供了一种用于在半导体衬底[36]之中和之上制造应力MOS器件[30]的方法。该方法包括以下步骤：形成覆盖半导体衬底[36]的栅极电极[66]并蚀刻半导体衬底中的第一沟槽[82]和第二沟槽[84]，第一沟槽和第二沟槽对准与门电极[66]。在第一沟槽[82]和第二沟槽[84]中选择性地生长应力诱导材料[90]，并将导电性确定杂质离子注入到应力诱导材料[90]中，以形成源极区[92] 第一沟槽[82]和第二沟槽[84]中的漏极区[94]。为了保持衬底中产生的应力，在离子注入步骤之后，在应力诱导材料[90]上沉积一层机械硬材料[96]。

7. 发明申请

WO2016081356A1 HIGH RESISTIVITY SEMICONDUCTOR-ON-INSULATOR WAFER AND A METHOD OF MANUFACTURING 审中-公开
标题翻译：高电阻半导体绝缘体波形及其制造方法
公开(公告)号：WO2016081356A1
公开(公告)日：2016-05-26
申请号：PCT/US2015/060854
申请日：2015-11-16
申请人： SUNEDISON SEMICONDUCTOR LIMITED , PEIDOUS, Igor
发明人： PEIDOUS, Igor , FEI, Lu , LIBBERT, Jeffrey Louis , JONES, Andrew M. , USENKO, Alex , WANG, Gang , THOMAS, Shawn G. , KOMMU, Srikanth
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
摘要翻译：提供了半导体绝缘体多层结构。多层包括高电阻率单晶半导体处理衬底，包括硅，锗或硅锗的任选松弛的半导体层，可选的多晶硅层，电介质层和单晶半导体器件层。

8. 发明申请

WO2012033574A3 METHODS TO ADJUST THRESHOLD VOLTAGE IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：在半导体器件中调节阈值电压的方法
公开(公告)号：WO2012033574A3
公开(公告)日：2012-05-03
申请号：PCT/US2011045320
申请日：2011-07-26
申请人： APPLIED MATERIALS INC , WARD MICHAEL G , PEIDOUS IGOR V , CHIANG SUNNY , TA YEN B , DARLAK ANDREW , PORSHNEV PETER I , SRINIVASAN SWAMINATHAN
发明人： WARD MICHAEL G , PEIDOUS IGOR V , CHIANG SUNNY , DARLAK ANDREW , PORSHNEV PETER I , SRINIVASAN SWAMINATHAN
IPC分类号： H01L21/336 , H01L21/8228 , H01L29/78
CPC分类号： H01L21/823842 , H01J37/32412 , H01L21/28088 , H01L21/28202 , H01L21/28229 , H01L29/78
摘要： Methods for forming a device on a substrate are provided herein. In some embodiments, a method of forming a device on a substrate may include providing a substrate having a partially fabricated first device disposed on the substrate, the first device including a first film stack comprising a first dielectric layer and a first high-k dielectric layer disposed atop the first dielectric layer; depositing a first metal layer atop the first film stack; and modifying a first upper surface of the first metal layer to adjust a first threshold voltage of the first device, wherein the modification of the first upper surface does not extend through to a first lower surface of the first metal layer.
摘要翻译：本文提供了在基板上形成器件的方法。在一些实施例中，在衬底上形成器件的方法可以包括提供具有设置在衬底上的部分制造的第一器件的衬底，第一器件包括第一膜堆叠，其包括第一介电层和第一高k电介质层设置在第一电介质层的顶部; 在第一薄膜叠层顶上沉积第一金属层; 以及修改所述第一金属层的第一上表面以调整所述第一器件的第一阈值电压，其中所述第一上表面的修改不延伸穿过所述第一金属层的第一下表面。

9. 发明申请

WO2012033574A2 METHODS TO ADJUST THRESHOLD VOLTAGE IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：调整半导体器件阈值电压的方法
公开(公告)号：WO2012033574A2
公开(公告)日：2012-03-15
申请号：PCT/US2011/045320
申请日：2011-07-26
申请人： APPLIED MATERIALS, INC. , WARD, Michael G. , PEIDOUS, Igor V. , CHIANG, Sunny , TA, Yen B. , DARLAK, Andrew , PORSHNEV, Peter I. , SRINIVASAN, Swaminathan
发明人： WARD, Michael G. , PEIDOUS, Igor V. , CHIANG, Sunny , DARLAK, Andrew , PORSHNEV, Peter I. , SRINIVASAN, Swaminathan
IPC分类号： H01L21/336 , H01L29/78 , H01L21/8228
CPC分类号： H01L21/823842 , H01J37/32412 , H01L21/28088 , H01L21/28202 , H01L21/28229 , H01L29/78
摘要： Methods for forming a device on a substrate are provided herein. In some embodiments, a method of forming a device on a substrate may include providing a substrate having a partially fabricated first device disposed on the substrate, the first device including a first film stack comprising a first dielectric layer and a first high-k dielectric layer disposed atop the first dielectric layer; depositing a first metal layer atop the first film stack; and modifying a first upper surface of the first metal layer to adjust a first threshold voltage of the first device, wherein the modification of the first upper surface does not extend through to a first lower surface of the first metal layer.
摘要翻译：本文提供了用于在衬底上形成器件的方法。在一些实施例中，在衬底上形成器件的方法可以包括提供衬底，该衬底具有设置在衬底上的部分制造的第一器件，第一器件包括第一膜叠层，该第一膜叠层包括第一电介质层和第一高k电介质层安置在第一介电层顶上; 在第一薄膜叠层上沉积第一金属层; 以及修改所述第一金属层的第一上表面以调整所述第一器件的第一阈值电压，其中所述第一上表面的所述修改不延伸到所述第一金属层的第一下表面。

10. 发明申请

WO2008063543A3 STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION 审中-公开
公开(公告)号：WO2008063543A3
公开(公告)日：2008-05-29
申请号：PCT/US2007/024034
申请日：2007-11-16
申请人： ADVANCED MICRO DEVICES, INC. , PAL, Rohit , PEIDOUS, Igor , BROWN, David
发明人： PAL, Rohit , PEIDOUS, Igor , BROWN, David
IPC分类号： H01L21/336 , H01L29/04
摘要： A stress enhanced MOS transistor [30] and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode [62] overlying and defining a channel region [68] in a monocrystalline semiconductor substrate [38]. A trench [72, 74] having a side surface [78, 80] facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material [82, 90] having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material [88, 100] having a second concentration of the substitutional atom. The second monocrystalline semiconductor material [82, 90] is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region [68] than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

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