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1. 发明申请

WO2010025391A2 INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：半导体衬底的集成光电二极管
公开(公告)号：WO2010025391A2
公开(公告)日：2010-03-04
申请号：PCT/US2009055408
申请日：2009-08-28
申请人： TAU METRIX INC , STEINBRUECK GARY L , VICKERS JAMES B , PELELLA MARIO M , AGHABABAZADEH MAJID
发明人： STEINBRUECK GARY L , VICKERS JAMES B , PELELLA MARIO M , AGHABABAZADEH MAJID
IPC分类号： H01L31/10
CPC分类号： H01L31/1016 , H01L27/1443 , H01L27/14603 , H01L27/14689 , H01L31/1037
摘要： A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.
摘要翻译：至少部分地制造成包括接触元件和材料的基板部分。衬底部分包括具有彼此相邻的重掺杂N型区域和重掺杂P型区域的掺杂区域。衬底的外表面具有包括透光区域的形貌，其中来自光源的光能够到达衬底的表面。将光施加到光透明区域上足以导致跨过重掺杂区域的结形成电压电势。衬底部分可以进一步包括一个或多个电触点，该一个或多个电触点位于衬底部分上以传导电流，该电流源于通过将光施加到光透明区域上而产生的电压电势到半导体衬底上的电路。

2. 发明申请

WO2007015930A1 METHODS FOR FABRICATING A STRESSED MOS DEVICE 审中-公开
标题翻译：用于制造受压MOS器件的方法
公开(公告)号：WO2007015930A1
公开(公告)日：2007-02-08
申请号：PCT/US2006/028171
申请日：2006-07-20
申请人： ADVANCED MICRO DEVICES, INC. , PEIDOUS, Igor , SULTAN, Akif , PELELLA, Mario, M.
发明人： PEIDOUS, Igor , SULTAN, Akif , PELELLA, Mario, M.
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods are provided for fabricating a stressed MOS device [30]. The method comprises the steps of forming a plurality of parallel MOS transistors in and on a semiconductor substrate [36]. The parallel MOS transistors having a common source [92] region, a common drain [94] region, and a common gate electrode [66]. A first trench [82] is etched into the substrate in the common source [92] region and a second trench [84] is etched into the substrate in the common drain [94] region. A stress inducing semiconductor material [90] that has a crystal lattice mismatched with the semiconductor substrate is selectively grown in the first [82] and second [84] trenches. The growth of the stress inducing material [90] creates both compressive longitudinal and tensile transverse stresses in the MOS device channel [50] that enhance the drive current of P-channel MOS transistors. The decrease in drive current of N-channel MOS transistors caused by the compressive stress component is offset by the tensile stress component.
摘要翻译：提供了制造应力MOS器件的方法[30]。该方法包括以下步骤：在半导体衬底上形成多个并联MOS晶体管[36]。并联MOS晶体管具有公共源极区域，公共漏极区域和公共栅极电极[66]。第一沟槽[82]被蚀刻到公共源极区域中的衬底中，并且第二沟槽[84]被蚀刻到公共漏极[94]区域中的衬底中。在第一[82]和第二[84]沟槽中选择性地生长具有与半导体衬底失配的晶格的应力诱导半导体材料[90]。应力诱导材料的生长[90]在MOS器件通道[50]中产生压缩纵向和拉伸横向应力，从而增强P沟道MOS晶体管的驱动电流。由压缩应力分量引起的N沟道MOS晶体管的驱动电流的减小由拉应力分量抵消。

3. 发明申请

WO2007126488A2 METHOD FOR FABRICATING A SEMICONDUCTOR COMPONENT INCLUDING A HIGH CAPACITANCE PER UNIT AREA CAPACITOR 审中-公开
标题翻译：用于制造包括每单位面积电容器的高电容的半导体元件的方法
公开(公告)号：WO2007126488A2
公开(公告)日：2007-11-08
申请号：PCT/US2007/004374
申请日：2007-02-20
申请人： ADVANCED MICRO DEVICES, INC. , PELELLA, Mario, M.
发明人： PELELLA, Mario, M.
IPC分类号： H01L27/06 , H01L21/84
CPC分类号： H01L27/0629 , H01L21/84 , H01L27/1203 , H01L28/55
摘要： A method is provided for fabricating a semiconductor component (20) that includes a capacitor (24) having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate (26) having a first semiconductor layer, a layer (32) of insulator (30) on the first semiconductor layer, and a second semiconductor layer (28) overlying the layer of insulator. The method comprises forming a first capacitor electrode (48) in the first semiconductor layer (32) and depositing a dielectric layer (52) comprising Ba|.x CaxTi)-Y ZrxO] overlying the first capacitor electrode (48). A conductive material is deposited and patterned to form a second capacitor electrode (54) overlying the dielectric layer (52), thus forming a capacitor (24) having a high dielectric constant dielectric (52). An MOS transistor (22) in then formed in a portion of the second semiconductor layer (28), the MOS transistor, and especially the gate dielectric (56) of the MOS transistor, formed independently of forming the capacitor and electrically isolated (38) from the capacitor.
摘要翻译：提供一种用于制造包括每单位面积具有高电容的电容器（24）的半导体部件（20）的方法。该部件形成在具有第一半导体层，第一半导体层上的绝缘体层（32）和第二半导体层（28）上的半导体绝缘体（SOI）基板（26）中，绝缘层。该方法包括在第一半导体层（32）中形成第一电容器电极（48），并沉积覆盖在第一电容器电极（48）上的包含Ba | .xCaxTi）-Y Zr x O的电介质层（52）。导电材料被沉积和图案化以形成覆盖介电层（52）的第二电容器电极（54），从而形成具有高介电常数电介质（52）的电容器（24）。然后形成在第二半导体层（28）的一部分中的MOS晶体管（22），MOS晶体管，特别是MOS晶体管的栅极电介质（56）独立于形成电容器并且电隔离（38）形成，从电容器。

4. 发明申请

WO2007126488A3 METHOD FOR FABRICATING A SEMICONDUCTOR COMPONENT INCLUDING A HIGH CAPACITANCE PER UNIT AREA CAPACITOR 审中-公开
标题翻译：用于制造包括每单位面积电容器的高电容的半导体元件的方法
公开(公告)号：WO2007126488A3
公开(公告)日：2008-01-31
申请号：PCT/US2007004374
申请日：2007-02-20
申请人： ADVANCED MICRO DEVICES INC , PELELLA MARIO M
发明人： PELELLA MARIO M
IPC分类号： H01L27/06 , H01L21/84
CPC分类号： H01L27/0629 , H01L21/84 , H01L27/1203 , H01L28/55
摘要： A method is provided for fabricating a semiconductor component (20) that includes a capacitor (24) having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate (26) having a first semiconductor layer, a layer (32) of insulator (30) on the first semiconductor layer, and a second semiconductor layer (28) overlying the layer of insulator. The method comprises forming a first capacitor electrode (48) in the first semiconductor layer (32) and depositing a dielectric layer (52) comprising Ba|.x CaxTi)-Y ZrxO] overlying the first capacitor electrode (48). A conductive material is deposited and patterned to form a second capacitor electrode (54) overlying the dielectric layer (52), thus forming a capacitor (24) having a high dielectric constant dielectric (52). An MOS transistor (22) in then formed in a portion of the second semiconductor layer (28), the MOS transistor, and especially the gate dielectric (56) of the MOS transistor, formed independently of forming the capacitor and electrically isolated (38) from the capacitor.
摘要翻译：提供一种用于制造包括每单位面积具有高电容的电容器（24）的半导体部件（20）的方法。该部件形成在具有第一半导体层，第一半导体层上的绝缘体层（32）和第二半导体层（28）上的半导体绝缘体（SOI）基板（26）中，绝缘层。该方法包括在第一半导体层（32）中形成第一电容器电极（48），并沉积覆盖在第一电容器电极（48）上的包含Ba | .xCaxTi）-Y Zr x O的电介质层（52）。导电材料被沉积和图案化以形成覆盖介电层（52）的第二电容器电极（54），从而形成具有高介电常数电介质（52）的电容器（24）。然后形成在第二半导体层（28）的一部分中的MOS晶体管（22），MOS晶体管，特别是MOS晶体管的栅极电介质（56）独立于形成电容器并且电隔离（38）形成，从电容器。

5. 发明申请

WO2005062357A1 STRAINED SEMICONDUCTOR SUBSTRATE AND PROCESSES THEREFOR 审中-公开
标题翻译：应变半导体衬底及其工艺
公开(公告)号：WO2005062357A1
公开(公告)日：2005-07-07
申请号：PCT/US2004/035417
申请日：2004-10-26
申请人： ADVANCED MICRO DEVICES, INC. , PELELLA, Mario, M. , CHAN, Simon, S.
发明人： PELELLA, Mario, M. , CHAN, Simon, S.
IPC分类号： H01L21/304
CPC分类号： H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/3043 , H01L29/7842
摘要： A method of manufacturing an integrated circuit (IC) utilizes a strained silicon (SMOS) substrate (20). The substrate (20) utilizes trenches (36) in a base layer to induce stress in a layer. The substrate can include silicon. The trenches (36) define pillars (35) on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.
摘要翻译：制造集成电路（IC）的方法利用应变硅（SMOS）衬底（20）。衬底（20）利用基层中的沟槽（36）在层中引起应力。衬底可以包括硅。沟槽（36）在绝缘体上半导体（SOI）晶片的体基板或基底层的背面上限定支柱（35）。

6. 发明申请

WO2010025391A3 INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES 审中-公开
公开(公告)号：WO2010025391A3
公开(公告)日：2010-03-04
申请号：PCT/US2009/055408
申请日：2009-08-28
申请人： TAU-METRIX, INC. , STEINBRUECK, Gary, L. , VICKERS, James, B. , PELELLA, Mario, M. , AGHABABAZADEH, Majid
发明人： STEINBRUECK, Gary, L. , VICKERS, James, B. , PELELLA, Mario, M. , AGHABABAZADEH, Majid
IPC分类号： H01L31/10
摘要： A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.

7. 发明申请

WO2007019002A2 METHODS FOR FABRICATING A STRESSED MOS DEVICE 审中-公开
标题翻译：用于制造受压MOS器件的方法
公开(公告)号：WO2007019002A2
公开(公告)日：2007-02-15
申请号：PCT/US2006/028197
申请日：2006-07-20
申请人： ADVANCED MICRO DEVICES, INC. , PEIDOUS, Igor , PELELLA, Mario, M.
发明人： PEIDOUS, Igor , PELELLA, Mario, M.
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A method for fabricating a stressed MOS device [30] in and on a semiconductor substrate [36] is provided. The method comprises the steps of forming a gate electrode [66] overlying the semiconductor substrate [36] and etching a first trench [82] and a second trench [84] in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode [66]. A stress inducing material [90] is selectively grown in the first trench [82] and in the second trench [84] and conductivity determining impurity ions are implanted into the stress inducing material [90] to form a source region [92] in the First trench [82] and a drain region [94] in the second trench [84]. To preserve the stress induced in the substrate, a layer of mechanically hard material [96] is deposited on the stress inducing material [90] after the step of ion implanting.
摘要翻译：提供了一种用于在半导体衬底[36]中和之上制造应力MOS器件[30]的方法。该方法包括以下步骤：在半导体衬底上形成覆盖半导体衬底[36]并蚀刻第一沟槽[82]和第二沟槽[84]的栅电极，第一沟槽和第二沟槽形成为对准与栅电极[66]。在第一沟槽[82]和第二沟槽[84]中选择性地生长应力诱导材料[90]，并且将导电性确定杂质离子注入到应力诱导材料[90]中以形成源极区域[92] 在第二沟槽[84]中的第一沟槽[82]和漏极区域[94]。为了保持在衬底中引起的应力，在离子注入步骤之后，将一层机械硬质材料沉积在应力诱导材料[90]上。

8. 发明申请

WO2006096433A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：WO2006096433A1
公开(公告)日：2006-09-14
申请号：PCT/US2006/007346
申请日：2006-02-28
申请人： ADVANCED MICRO DEVICES, INC. , PELELLA, Mario, M. , CHAN, Darin, A. , CHAN, Simon, S.
发明人： PELELLA, Mario, M. , CHAN, Darin, A. , CHAN, Simon, S.
IPC分类号： H01L21/84 , H01L27/12 , H01L21/762
CPC分类号： H01L21/823481 , H01L21/84 , H01L27/1203
摘要： A semiconductor component (10, 300) having analog and logic circuit elements manufactured from an SOI substrate (12) and a method for manufacturing the semiconductor component (10, 300). An SOI substrate (12) has a support wafer (14) coupled to an active wafer (18) through an insulating material (16). Openings (22, 24) are formed in the active wafer (18), extend through the insulating material (16), and expose portions of the support wafer (14). Epitaxial semiconductor material (26) is grown on the exposed portions of the support wafer (14). Analog circuitry is manufactured from the epitaxially grown semiconductor material (26) and high performance logic circuitry is manufactured from the active wafer (18). The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact (246, 266) is made from a portion of the epitaxially grown semiconductor material (26) that is electrically isolated from the portion in which the analog circuitry is manufactured.
摘要翻译：具有由SOI衬底（12）制造的模拟和逻辑电路元件的半导体元件（10,300）和用于制造半导体元件（10,300）的方法。 SOI衬底（12）具有通过绝缘材料（16）耦合到有源晶片（18）的支撑晶片（14）。开口（22,24）形成在活动晶片（18）中，延伸穿过绝缘材料（16），并暴露支撑晶片（14）的部分。在支撑晶片（14）的暴露部分上生长外延半导体材料（26）。由外延生长的半导体材料（26）制造模拟电路，并且由活性晶片（18）制造高性能逻辑电路。用于制造模拟电路的处理步骤与用于制造高性能逻辑电路的步骤分离。衬底接触（246,266）由外延生长的半导体材料（26）的与制造模拟电路的部分电绝缘的部分制成。

9. 发明申请

WO2008011144A1 SOI DEVICE AND METHOD FOR ITS FABRICATION 审中-公开
标题翻译： SOI器件及其制造方法
公开(公告)号：WO2008011144A1
公开(公告)日：2008-01-24
申请号：PCT/US2007/016453
申请日：2007-07-20
申请人： ADVANCED MICRO DEVICES, INC. , PELELLA, Mario, M. , WU, Donggang, D. , BULLER, James, F.
发明人： PELELLA, Mario, M. , WU, Donggang, D. , BULLER, James, F.
IPC分类号： H01L27/02
CPC分类号： H01L27/0255 , H01L21/743 , H01L21/84 , H01L27/1203
摘要： A silicon on insulator (SOI) device [53] and methods for fabricating such a device are provided. The device includes an MOS capacitor [52] coupled between voltage busses [100, 102] and formed in a monocrystalline semiconductor layer [30] overlying an insulator layer [32] and a semiconductor substrate [34]. The device includes at least one electrical discharge path [86, 98, 180, 178] for discharging potentially harmful charge build up on the MOS capacitor [52]. The MOS capacitor has a conductive electrode material forming a first plate [64] of the MOS capacitor and an impurity doped region [60] in the monocrystalline silicon layer [30] beneath the conductive electrode material forming a second plate. A first voltage bus [100] is coupled to the first plate [64] of the capacitor and to an electrical discharge path through a diode [177] formed in the semiconductor substrate and a second voltage bus [102] is coupled to the second plate [60] of the capacitor.
摘要翻译：提供了绝缘体上硅（SOI）器件[53]和制造这种器件的方法。该器件包括耦合在电压总线[100,102]之间并形成在覆盖绝缘体层[32]和半导体衬底[34]的单晶半导体层[30]中的MOS电容器[52]。该装置包括至少一个放电路径[86,98,180,178]，用于在MOS电容器[52]上放电潜在的有害电荷。 MOS电容器具有形成MOS电容器的第一板[64]的导电电极材料和形成第二板的导电电极材料下面的单晶硅层[30]中的杂质掺杂区域[60]。第一电压总线[100]耦合到电容器的第一板[64]和通过形成在半导体衬底中的二极管（177）的放电路径，并且第二电压总线[102]耦合到第二板 [60]电容器。

10. 发明申请

WO2007019002A3 METHODS FOR FABRICATING A STRESSED MOS DEVICE 审中-公开
标题翻译：制造应力MOS器件的方法
公开(公告)号：WO2007019002A3
公开(公告)日：2007-03-29
申请号：PCT/US2006028197
申请日：2006-07-20
申请人： ADVANCED MICRO DEVICES INC , PEIDOUS IGOR , PELELLA MARIO M
发明人： PEIDOUS IGOR , PELELLA MARIO M
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A method for fabricating a stressed MOS device [30] in and on a semiconductor substrate [36] is provided. The method comprises the steps of forming a gate electrode [66] overlying the semiconductor substrate [36] and etching a first trench [82] and a second trench [84] in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode [66]. A stress inducing material [90] is selectively grown in the first trench [82] and in the second trench [84] and conductivity determining impurity ions are implanted into the stress inducing material [90] to form a source region [92] in the First trench [82] and a drain region [94] in the second trench [84]. To preserve the stress induced in the substrate, a layer of mechanically hard material [96] is deposited on the stress inducing material [90] after the step of ion implanting.
摘要翻译：提供了一种用于在半导体衬底[36]之中和之上制造应力MOS器件[30]的方法。该方法包括以下步骤：形成覆盖半导体衬底[36]的栅极电极[66]并蚀刻半导体衬底中的第一沟槽[82]和第二沟槽[84]，第一沟槽和第二沟槽对准与门电极[66]。在第一沟槽[82]和第二沟槽[84]中选择性地生长应力诱导材料[90]，并将导电性确定杂质离子注入到应力诱导材料[90]中，以形成源极区[92] 第一沟槽[82]和第二沟槽[84]中的漏极区[94]。为了保持衬底中产生的应力，在离子注入步骤之后，在应力诱导材料[90]上沉积一层机械硬材料[96]。

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