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    • 1. 发明申请
    • METHODS FOR THE OPTIMIZATION OF SUBSTRATE ETCHING IN A PLASMA PROCESSING SYSTEM
    • 在等离子体处理系统中优化基板蚀刻的方法
    • WO2005091974A3
    • 2006-09-21
    • PCT/US2005007886
    • 2005-03-09
    • LAM RES CORPKIM JISOOWORSHAM BINETYEN BI-MINGLOEWENHARDT PETER K
    • KIM JISOOWORSHAM BINETYEN BI-MINGLOEWENHARDT PETER K
    • C23F1/00B44C1/22C03C15/00H01L21/302H01L21/311H01L21/768
    • H01L21/31144H01L21/76811H01L21/76813
    • A method of etching a substrate in a plasma processing system is disclosed. The substrate has a semi-conductor layer, a first barrier layer disposed above the semi-conductor layer, a low-k layer disposed above the first barrier layer, a third hard mask layer disposed above the low-k layer; a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer. The method includes alternatively etching the substrate with a first etchant and a second etchant, wherein the first etchant has a low selectivity to a first hard mask material of the first hard mask layer, a third hard mask material of the a third hard mask layer, and a first barrier layer material of the first barrier layer, but a high selectivity to a second hard mask material of the second hard mask layer; and wherein the second etchant has a high selectivity to the first hard mask material of the first hard mask layer, the third hard mask material of the third hard mask layer, and the first barrier layer material of the first barrier layer, and the first etchant has a low selectivity to the second hard mask material of the second hard mask layer.
    • 公开了一种在等离子体处理系统中蚀刻衬底的方法。 衬底具有半导体层,设置在半导体层上方的第一势垒层,设置在第一阻挡层上方的低k层,设置在低k层上方的第三硬掩模层; 设置在第三硬掩模层之上的第二硬掩模层,以及设置在第二硬掩模层上方的第一硬掩模层。 所述方法包括用第一蚀刻剂和第二蚀刻剂替代地蚀刻所述衬底,其中所述第一蚀刻剂对所述第一硬掩模层的第一硬掩模材料具有低选择性,所述第三硬掩模层的第三硬掩模材料, 和第一阻挡层的第一阻挡层材料,但对第二硬掩模层的第二硬掩模材料具有高选择性; 并且其中第二蚀刻剂对第一硬掩模层的第一硬掩模材料,第三硬掩模层的第三硬掩模材料和第一阻挡层的第一阻挡层材料和第一蚀刻剂具有高选择性 对第二硬掩模层的第二硬掩模材料具有低选择性。
    • 3. 发明申请
    • METHODS FOR THE OPTIMIZATION OF SUBSTRATE ETCHING IN A PLASMA PROCESSING SYSTEM
    • 一种等离子体处理系统中基片蚀刻的优化方法
    • WO2005091974A2
    • 2005-10-06
    • PCT/US2005/007886
    • 2005-03-09
    • LAM RESEARCH CORPORATIONKIM, JisooWORSHAM, BinetYEN, Bi-MingLOEWENHARDT, Peter K.
    • KIM, JisooWORSHAM, BinetYEN, Bi-MingLOEWENHARDT, Peter K.
    • B44C1/22C03C15/00C23F1/00H01L21/302H01L21/311H01L21/768
    • H01L21/31144H01L21/76811H01L21/76813
    • A method of etching a substrate in a plasma processing system is disclosed. The substrate has a semi-conductor layer, a first barrier layer disposed above the semi-conductor layer, a low-k layer disposed above the first barrier layer, a third hard mask layer disposed above the low-k layer; a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer. The method includes alternatively etching the substrate with a first etchant and a second etchant, wherein the first etchant has a low selectivity to a first hard mask material of the first hard mask layer, a third hard mask material of the a third hard mask layer, and a first barrier layer material of the first barrier layer, but a high selectivity to a second hard mask material of the second hard mask layer; and wherein the second etchant has a high selectivity to the first hard mask material of the first hard mask layer, the third hard mask material of the third hard mask layer, and the first barrier layer material of the first barrier layer, and the first etchant has a low selectivity to the second hard mask material of the second hard mask layer.
    • 公开了一种在等离子体处理系统中蚀刻衬底的方法。 衬底具有半导体层,设置在半导体层上方的第一阻挡层,设置在第一阻挡层上方的低k层,设置在低k层上方的第三硬掩模层, 设置在第三硬掩模层上方的第二硬掩模层以及设置在第二硬掩模层上方的第一硬掩模层。 该方法包括用第一蚀刻剂和第二蚀刻剂交替地蚀刻衬底,其中第一蚀刻剂对第一硬掩模层的第一硬掩模材料,第三硬掩模层的第三硬掩模材料, 以及第一阻挡层的第一阻挡层材料,但对第二硬掩模层的第二硬掩模材料具有高选择性; 且其中所述第二蚀刻剂对所述第一硬掩模层的所述第一硬掩模材料,所述第三硬掩模层的所述第三硬掩模材料以及所述第一势垒层的所述第一势垒层材料具有高选择性,并且所述第一蚀刻剂 对第二硬掩模层的第二硬掩模材料具有低选择性。
    • 5. 发明申请
    • METHODS FOR PREVENTING CORROSION OF PLASMA-EXPOSED YTTRIA COATED CONSTITUENTS
    • 防止等离子暴露的YTTRIA涂层成分腐蚀的方法
    • WO2012020355A3
    • 2012-06-07
    • PCT/IB2011053459
    • 2011-08-03
    • LAM RES CORPLAM RES AGSWAMI GANAPATHYLOEWENHARDT PETERYUNSANG KIM
    • SWAMI GANAPATHYLOEWENHARDT PETERYUNSANG KIM
    • H01L21/205
    • C23C16/4404
    • In accordance with one embodiment of the present disclosure, a method for preventing corrosion of a plasma-exposed yttria-coated constituent from ambient acidic hydrolysis wherein the plasma-exposed yttria-coated constituent includes a hydrolysable acid precursor is disclosed. The method may include: removing the plasma-exposed yttria-coated constituent from a semiconductor processing assembly; binding the plasma-exposed yttria-coated constituent with flexible moisture wicking material; hydrolyzing the hydrolysable acid precursor with an overwhelming aqueous admixture to form a vitiated acidic compound, wherein the flexible moisture wicking material pulls the vitiated acidic compound away from the plasma-exposed yttria-coated constituent with capillary action; dehydrating the plasma-exposed yttria-coated constituent with additional flexible moisture wicking material to pull a latent amount of the vitiated acidic compound away from the plasma-exposed yttria-coated constituent; and isolating the plasma-exposed yttria-coated constituent from ambient moisture in a moisture obstructing enclosure.
    • 根据本公开的一个实施方式,公开了防止暴露于等离子体的氧化钇涂覆的组分从环境酸性水解腐蚀的方法,其中等离子体暴露的氧化钇涂覆的组分包含可水解的酸前体。 该方法可以包括:从半导体加工组件移除暴露于等离子体的氧化钇涂覆的成分; 将暴露于等离子体的氧化钇涂覆的成分与挠性吸湿材料结合; 用压倒性含水混合物水解可水解酸前体以形成沾污的酸性化合物,其中柔性吸湿材料利用毛细管作用将沾污的酸性化合物从暴露于等离子体的氧化钇涂覆的成分拉开; 用额外的挠性吸湿材料使暴露于等离子体的氧化钇涂覆的组分脱水以将潜在量的腐蚀的酸性化合物从暴露于氧化钇的等离子体涂覆的组分上移开; 以及在潮湿阻挡外壳中将暴露于等离子体的氧化钇涂覆的成分与环境湿气分离。
    • 6. 发明申请
    • METHODS FOR THE OPTIMIZATION OF SUBSTRATE ETCHING IN A PLASMA PROCESSING SYSTEM
    • 在等离子体处理系统中优化基板蚀刻的方法
    • WO2005091974A9
    • 2005-11-24
    • PCT/US2005007886
    • 2005-03-09
    • LAM RES CORPKIM JISOOWORSHAM BINETYEN BI-MINGLOEWENHARDT PETER K
    • KIM JISOOWORSHAM BINETYEN BI-MINGLOEWENHARDT PETER K
    • B44C1/22C03C15/00C23F1/00H01L21/302H01L21/311H01L21/768
    • H01L21/31144H01L21/76811H01L21/76813
    • A method of etching a substrate in a plasma processing system is disclosed. The substrate has a semi-conductor layer, a first barrier layer disposed above the semi-conductor layer, a low-k layer disposed above the first barrier layer, a third hard mask layer disposed above the low-k layer; a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer. The method includes alternatively etching the substrate with a first etchant and a second etchant, wherein the first etchant has a low selectivity to a first hard mask material of the first hard mask layer, a third hard mask material of the a third hard mask layer, and a first barrier layer material of the first barrier layer, but a high selectivity to a second hard mask material of the second hard mask layer; and wherein the second etchant has a high selectivity to the first hard mask material of the first hard mask layer, the third hard mask material of the third hard mask layer, and the first barrier layer material of the first barrier layer, and the first etchant has a low selectivity to the second hard mask material of the second hard mask layer.
    • 公开了一种在等离子体处理系统中蚀刻衬底的方法。 衬底具有半导体层,设置在半导体层上方的第一势垒层,设置在第一阻挡层上方的低k层,设置在低k层上方的第三硬掩模层; 设置在第三硬掩模层之上的第二硬掩模层,以及设置在第二硬掩模层上方的第一硬掩模层。 所述方法包括用第一蚀刻剂和第二蚀刻剂替代地蚀刻所述衬底,其中所述第一蚀刻剂对所述第一硬掩模层的第一硬掩模材料具有低选择性,所述第三硬掩模层的第三硬掩模材料, 和第一阻挡层的第一阻挡层材料,但对第二硬掩模层的第二硬掩模材料具有高选择性; 并且其中第二蚀刻剂对第一硬掩模层的第一硬掩模材料,第三硬掩模层的第三硬掩模材料和第一阻挡层的第一阻挡层材料和第一蚀刻剂具有高选择性 对第二硬掩模层的第二硬掩模材料具有低选择性。