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1. 发明申请

WO2006065759A2 DUAL STRESSED SOI SUBSTRATES 审中-公开
标题翻译：双应力SOI衬底
公开(公告)号：WO2006065759A2
公开(公告)日：2006-06-22
申请号：PCT/US2005/044957
申请日：2005-12-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , DOKUMACI, Omer, H. , DORIS, Bruce, B. , GLUSCHENKOV, Oleg , ZHU, Huilong
发明人： CHIDAMBARRAO, Dureseti , DOKUMACI, Omer, H. , DORIS, Bruce, B. , GLUSCHENKOV, Oleg , ZHU, Huilong
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

2. 发明申请

WO2006065759A3 DUAL STRESSED SOI SUBSTRATES 审中-公开
标题翻译：双应力SOI衬底
公开(公告)号：WO2006065759A3
公开(公告)日：2007-06-14
申请号：PCT/US2005044957
申请日：2005-12-13
申请人： IBM , CHIDAMBARRAO DURESETI , DOKUMACI OMER H , DORIS BRUCE B , GLUSCHENKOV OLEG , ZHU HUILONG
发明人： CHIDAMBARRAO DURESETI , DOKUMACI OMER H , DORIS BRUCE B , GLUSCHENKOV OLEG , ZHU HUILONG
IPC分类号： H01L21/84 , H01L27/01
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

3. 发明申请

WO2005067035A1 METHOD FOR FORMING NON-AMORPHOUS, ULTRA-THIN SEMICONDUCTOR DEVICES USING SACRIFICIAL IMPLANTATION LAYER 审中-公开
标题翻译：使用非正式植入层形成非 - 非晶，超薄半导体器件的方法
公开(公告)号：WO2005067035A1
公开(公告)日：2005-07-21
申请号：PCT/US2003/038559
申请日：2003-12-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DOKUMACI, Omer, H. , RONSHEIM, Paul
发明人： DOKUMACI, Omer, H. , RONSHEIM, Paul
IPC分类号： H01L21/8242
CPC分类号： H01L29/6659 , H01L21/2254 , H01L21/2255 , H01L21/26513 , H01L21/28114 , H01L29/1083 , H01L29/42376 , H01L29/665 , H01L29/66628 , H01L29/66772 , H01L29/66795 , H01L29/785
摘要： A method for forming a semiconductor device includes defining a sacrificial layer (108) over a single crystalline substrate (106). The sacrificial layer (108) is implanted with a dopant species in a manner that prevents the single crystalline substrate (106) from becoming substantially amorphized. The sacrificial layer (108) is annealed so as to drive said dopant species from said sacrificial layer (108) into said single crystalline substrate (106).
摘要翻译：用于形成半导体器件的方法包括在单晶衬底（106）上限定牺牲层（108）。牺牲层（108）以防止单晶衬底（106）变得基本非晶化的方式注入掺杂剂物质。牺牲层（108）被退火以便将所述掺杂剂物质从所述牺牲层（108）驱动到所述单晶衬底（106）中。

4. 发明申请

WO2005057612A3 SILICON DEVICE ON Si:C-OI and SGOI AND METHOD OF MANUFACTURE 审中-公开
标题翻译： Si：C-OI和SGOI上的硅器件及其制造方法
公开(公告)号：WO2005057612A3
公开(公告)日：2008-01-03
申请号：PCT/US2004020904
申请日：2004-06-30
申请人： IBM , CHIDAMBARRAO DURESETI , DOKUMACI OMER H , GLUSCHENKOV OLEG G
发明人： CHIDAMBARRAO DURESETI , DOKUMACI OMER H , GLUSCHENKOV OLEG G
IPC分类号： H01L21/8238 , H01L21/311 , H01L21/76 , H01L21/82 , H01L21/84 , H01L27/12 , H01L29/24 , H01L29/808
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) (25) in a substrate and providing a first material (30) and a second material (40) on the substrate. The first material (30) and the second material (40) are mixed into the substrate by a thermal anneal process to form a first island (50) and second island (55) at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island (50) and the second island (55). The STI relaxes and facilitates the relaxation of the first island (50) and the second island (55). The first material (30) may be deposited or grown Ge material and the second material (40) may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island (50) and the second island (55).
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI）（25），并在衬底上提供第一材料（30）和第二材料（40）。通过热退火工艺将第一材料（30）和第二材料（40）混合到衬底中，以在nFET区域和pFET区域分别形成第一岛（50）和第二岛（55）。在第一岛（50）和第二岛（55）上形成不同材料层。 STI放松并促进第一个岛屿（50）和第二个岛屿（55）的放松。可以将第一材料（30）沉积或生长Ge材料，并且第二材料（40）可以沉积或生长Si：C或C.在第一岛（50）和第二岛（50）中的至少一个上形成应变Si层岛（55）。

5. 发明申请

WO2005057612A2 SILICON DEVICE ON Si:C-OI and SGOI AND METHOD OF MANUFACTURE 审中-公开
标题翻译： Si：C-OI和SGOI上的硅器件及其制造方法
公开(公告)号：WO2005057612A2
公开(公告)日：2005-06-23
申请号：PCT/US2004/020904
申请日：2004-06-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , DOKUMACI, Omer, H. , GLUSCHENKOV, Oleg, G.
发明人： CHIDAMBARRAO, Dureseti , DOKUMACI, Omer, H. , GLUSCHENKOV, Oleg, G.
IPC分类号： H01L
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) (25) in a substrate and providing a first material (30) and a second material (40) on the substrate. The first material (30) and the second material (40) are mixed into the substrate by a thermal anneal process to form a first island (50) and second island (55) at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island (50) and the second island (55). The STI relaxes and facilitates the relaxation of the first island (50) and the second island (55). The first material (30) may be deposited or grown Ge material and the second material (40) may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island (50) and the second island (55).
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI）（25），并在衬底上提供第一材料（30）和第二材料（40）。通过热退火工艺将第一材料（30）和第二材料（40）混合到衬底中，以在nFET区域和pFET区域分别形成第一岛（50）和第二岛（55）。在第一岛（50）和第二岛（55）上形成不同材料层。 STI放松并促进第一个岛屿（50）和第二个岛屿（55）的放松。可以将第一材料（30）沉积或生长Ge材料，并且第二材料（40）可以沉积或生长Si：C或C.在第一岛（50）和第二岛（50）中的至少一个上形成应变Si层岛（55）。

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