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1. 发明申请

WO2020236237A1 TIME INTERLEAVED PHASED ARRAY RECEIVERS 审中-公开
公开(公告)号：WO2020236237A1
公开(公告)日：2020-11-26
申请号：PCT/US2020/019503
申请日：2020-02-24
申请人： ADESTO TECHNOLOGIES CORPORATION
发明人： O'SULLIVAN, Cormac , TARDIVEL, Benjamin , MARQUE, Joao
IPC分类号： H04B1/707 , H04B7/10 , H04B1/04 , H04L1/02
摘要： A phased array receiver can include a plurality of antennas, a plurality of compound analog-to-digital converters and a beam former. The plurality of antennas can be arranged in an array. The plurality of compound analog-to-digital converters can include respective inputs coupled to respective ones of the plurality of antennas. Respective output of the plurality of compound analog-to-digital converters can be coupled to the beam former. Each compound analog-to-digital converter can include a plurality of time interleaved sub-analog-to-digital converters. Sampling by the sub- analog-to-digital converters can be random between the sub-analog-to-digital converters within respective compound analog-to-digital converters and random between die plurality of compound analog-to-digital converters. In addition, dynamic element mismatch using a random bitstream generator can be employed in digital-to-analog converters and analog-to-digital converters.

2. 发明申请

WO2017031027A1 OFFSET TEST PADS FOR WLCSP FINAL TEST 审中-公开
标题翻译：用于WLCSP最终测试的偏移测试垫
公开(公告)号：WO2017031027A1
公开(公告)日：2017-02-23
申请号：PCT/US2016/046968
申请日：2016-08-15
申请人： ADESTO TECHNOLOGIES CORPORATION
发明人： PEDERSEN, Bard, M.
IPC分类号： H01L23/12 , H01L23/50 , H01L23/498 , H01L21/768
CPC分类号： H01L23/50 , H01L22/32 , H01L23/12 , H01L23/498 , H01L2224/11
摘要： A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball.
摘要翻译：配置用于WLCSP的设备可以包括：第一焊盘; 测试垫偏离第一焊盘; 将第一焊盘连接到测试焊盘的第一RDL路径; 以及将测试垫连接到焊球的第二RDL路径。在另一种情况下，配置用于WLCSP的设备可以包括：第一焊盘; 测试垫偏离第一焊盘; 将第一焊盘连接到焊球的第一RDL路径; 以及将测试焊盘连接到焊球的第二RDL路径。具有被配置用于WLCSP的器件的晶片可以包括：具有第一焊盘的第一器件; 具有测试垫的第二设备; 将第一焊盘连接到焊球的第一RDL路径; 以及将测试焊盘连接到焊球的第二RDL路径。

3. 发明申请

WO2014043137A1 RESISTIVE DEVICES AND METHODS OF OPERATION THEREOF 审中-公开
标题翻译：电阻器件及其操作方法
公开(公告)号：WO2014043137A1
公开(公告)日：2014-03-20
申请号：PCT/US2013/059083
申请日：2013-09-10
申请人： ADESTO TECHNOLOGIES CORPORATION
发明人： KOUSHAN, Foroozan Sarah , VAN BUSKIRK, Michael A.
IPC分类号： G11C11/24
CPC分类号： G11C13/0011 , G11C11/24 , G11C13/0023 , G11C13/003 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2213/74 , G11C2213/79
摘要： A method of operating a memory cell can include applying a select pulse at a gate of a select transistor having a first node and a second node, the first node coupled to the first access terminal of the access device, wherein the second node is coupled to a bit line potential node; charging a capacitor having a first plate and a second plate, the first plate coupled to the first node of the select transistor and to the first access terminal of the access device during the select pulse; activating the access device after charging the capacitor; deactivating the select transistor after activating the access device; and discharging the charged capacitor through the resistive switching device.
摘要翻译：操作存储器单元的方法可以包括在具有第一节点和第二节点的选择晶体管的栅极处施加选择脉冲，第一节点耦合到接入设备的第一接入终端，其中第二节点耦合到位线势点; 对具有第一板和第二板的电容器充电，所述第一板耦合到选择晶体管的第一节点并且在选择脉冲期间耦合到接入装置的第一接入终端; 在对电容器充电后激活接入设备; 激活接入设备后去激活选择晶体管; 并通过电阻式开关装置对充电的电容器进行放电。

4. 发明申请

WO2013148777A1 MEMORY DEVICES AND METHODS HAVING ADAPTABLE READ THRESHOLD LEVELS 审中-公开
标题翻译：具有适应性读取阈值水平的存储器件和方法
公开(公告)号：WO2013148777A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/034015
申请日：2013-03-27
申请人： ADESTO TECHNOLOGIES CORPORATION , GOPINATH, Venkatesh, P. , KOUSHAN, Foroozan, Sarah , LEWIS, Derric, Jawaher, Herman
发明人： GOPINATH, Venkatesh, P. , KOUSHAN, Foroozan, Sarah , LEWIS, Derric, Jawaher, Herman
IPC分类号： H01L47/00
CPC分类号： G11C13/004 , G11C11/5614 , G11C13/0011 , G11C13/0035 , G11C13/0064 , G11C13/0069 , G11C16/28
摘要： A method can include determining at least one use characteristic for the memory cells comprising a solid electrolyte, the use characteristic corresponding to a number of times the memory cells have been programmed to at least one impedance level; and adjusting a read threshold level for the memory cells based on at least the use characteristic, the read threshold level determining data values stored in the memory cells in a read operation.
摘要翻译：一种方法可以包括确定包括固体电解质的存储单元的至少一个使用特性，所述使用特性对应于存储器单元已被编程至少一个阻抗水平的次数; 以及至少基于所述使用特性来调整所述存储器单元的读取阈值电平，所述读取阈值电平确定在读取操作中存储在所述存储器单元中的数据值。

5. 发明申请

WO2017151665A1 READ LATENCY REDUCTION IN A MEMORY DEVICE 审中-公开
标题翻译：读取存储设备中的延迟时间
公开(公告)号：WO2017151665A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/020021
申请日：2017-02-28
申请人： ADESTO TECHNOLOGIES CORPORATION
发明人： INTRATER, Gideon , PEDERSEN, Bard , NAVEH, Ishai
IPC分类号： G11C7/06 , G11C7/10 , G11C7/22 , G11C8/06
CPC分类号： G11C8/06 , G11C5/066 , G11C7/062 , G11C7/103 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C29/021 , G11C29/028 , G11C2029/0409 , G11C2029/5006
摘要： A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.
摘要翻译：存储器件可以包括：具有排列为数据线的存储单元的存储器阵列; 接口，其从起始字节的地址以连续寻址的顺序接收请求字节数据的读命令; 第一缓冲器，其存储来自所述存储器阵列的包括所述起始字节的第一数据线; 第二缓冲器，其存储来自所述存储器阵列的第二数据线，所述第二数据线相对于所述第一数据线被连续寻址; 输出电路，被配置为访问来自缓冲器的数据，并且从起始字节顺序地输出每个字节通过第一数据线的最高寻址字节，并且每个字节从第二数据线的最低寻址字节开始直到所请求的数据字节具有已输出; 以及一个数据选通驱动器，用于为接口上的数据选通器输出的每个字节的数据输出时钟。

6. 发明申请

WO2017034852A1 AUTOMATIC SWITCH TO SINGLE SPI MODE WHEN ENTERING UDPD 审中-公开
标题翻译：在输入UDPD时自动切换到单模SPI模式
公开(公告)号：WO2017034852A1
公开(公告)日：2017-03-02
申请号：PCT/US2016/047128
申请日：2016-08-16
申请人： ADESTO TECHNOLOGIES CORPORATION
发明人： PEDERSEN, Bard, M.
IPC分类号： G11C5/14
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0625 , G06F3/0634 , G06F3/0679 , G11C5/148
摘要： A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; switching the interface to a Single SPI mode in response to the write command and the AUDPD configuration bit being set; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.
摘要翻译：一种在存储设备中控制超深度掉电（UDPD）模式的方法可以包括：经由接口从主机接收写命令; 在存储器装置上开始写入操作以执行写入命令; 从状态寄存器读取自动UDPD（AUDPD）配置位; 响应于写命令和AUDPD配置位置1，将接口切换到单SPI模式; 完成对存储设备的写入操作; 响应于设置了AUDPD配置位，在完成写操作时自动进入UDPD模式; 并且响应于AUDPD配置位被清除而在完成写操作时进入待机模式。

7. 发明申请

WO2016133661A1 RESISTIVE SWITCHING MEMORY WITH CELL ACCESS BY ANALOG SIGNAL CONTROLLED TRANSMISSION GATE 审中-公开
标题翻译：通过模拟信号控制传输门的电容接入电阻开关存储器
公开(公告)号：WO2016133661A1
公开(公告)日：2016-08-25
申请号：PCT/US2016/014970
申请日：2016-01-26
申请人： ADESTO TECHNOLOGIES CORPORATION
发明人： GOPINATH, Venkatesh, P. , KAMALANATHAN, Deepak , WANG, Daniel
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0002 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2213/74 , G11C2213/79
摘要： In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.
摘要翻译：在一个实施例中，半导体存储器件包括多个电阻式开关存储器单元，其中每个电阻式开关存储器单元可以包括：（i）具有阳极和阴极的可编程阻抗元件; （ii）被配置为控制对所述可编程阻抗元件的访问的字线对，其中所述字线对包括第一和第二字线; （iii）具有耦合到阴极的源极，耦合到位线的漏极和耦合到第一字线的栅极的PMOS晶体管; 以及（iv）具有耦合到所述位线的源极，耦合到所述阴极的漏极和耦合到所述第二字线的栅极的NMOS晶体管。

8. 发明申请

WO2014137943A2 PROGRAMMABLE IMPEDANCE MEMORY ELEMENTS AND CORRESPONDING METHODS 审中-公开
标题翻译：可编程阻抗记忆元素和相关方法
公开(公告)号：WO2014137943A2
公开(公告)日：2014-09-12
申请号：PCT/US2014/020034
申请日：2014-03-03
申请人： ADESTO TECHNOLOGIES CORPORATION
发明人： LEE, Wei Ti , WANG, Janet , GOPALAN, Chakravarthy , SHIELDS, Jeffrey Allan , MA, Yi , TSAI, Kuei Chang , SANCHEZ, John , JAMESON, John Ross , VAN BUSKIRK, Michael A. , GOPINATH, Venkatesh P.
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： H01L45/08 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16
摘要： A memory element programmable between different impedance states can include a first electrode; a switching layer formed in contact with the first electrode and including at least one metal oxide; and a buffer layer in contact with the switching layer. A buffer layer can include a first metal, tellurium, a third element, and a second metal distributed within the buffer layer. A second electrode can be in contact with the buffer layer.
摘要翻译：可编程在不同阻抗状态之间的存储元件可包括第一电极; 开关层，与所述第一电极接触并且包括至少一种金属氧化物; 以及与开关层接触的缓冲层。缓冲层可以包括分布在缓冲层内的第一金属，碲，第三元素和第二金属。第二电极可以与缓冲层接触。

9. 发明申请

WO2013170214A2 RESISTIVE DEVICES AND METHODS OF OPERATION THEREOF 审中-公开
标题翻译：电阻器件及其操作方法
公开(公告)号：WO2013170214A2
公开(公告)日：2013-11-14
申请号：PCT/US2013/040652
申请日：2013-05-10
申请人： ADESTO TECHNOLOGIES CORPORATION , AXON TECHNOLOGIES CORPORATION
发明人： KAMALANATHAN, Deepak , KOUSHAN, Foroozan, Sarah , ECHEVERRY, Juan, Pablo, Saenz , DINH, John , HOLLMER, Shane, C. , KOZICKI, Michael
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0092 , G11C2213/79
摘要： In one embodiment, a method of operating a resistive switching device 10 includes applying a signal comprising a pulse on a first terminal 1 of a two terminal resistive switching device10 having the first terminal 1 and a second terminal 2. The resistive switching device 10 has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.
摘要翻译：在一个实施例中，一种操作电阻式开关装置10的方法包括在具有第一端子1的二端电阻式开关装置10和第二端子2的第一端子1上施加包括脉冲的信号。电阻式开关装置10具有第一状态和第二状态。脉冲包括在第一时间段内从第一电压到第二电压的第一斜坡。第一时间段是脉冲总时间的至少0.1倍。

10. 发明申请

WO2013039603A1 RESISTIVE SWITCHING DEVICES HAVING ALLOYED ELECTRODES AND METHODS OF FORMATION THEREOF 审中-公开
标题翻译：具有合金电极的电阻开关器件及其形成方法
公开(公告)号：WO2013039603A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/046745
申请日：2012-07-13
申请人： ADESTO TECHNOLOGIES CORPORATION , ADESTO TECHNOLOGIES FRANCE SARL , RAMBUS, INC. , LEE, Wei Ti , GOPALAN, Chakravarthy , MA, Yi , SHIELDS, Jeffrey , BLANCHARD, Philippe , JAMESON, John Ross , KOUSHAN, Foroozan Sarah , WANG, Janet , KELLAM, Mark
发明人： LEE, Wei Ti , GOPALAN, Chakravarthy , MA, Yi , SHIELDS, Jeffrey , BLANCHARD, Philippe , JAMESON, John Ross , KOUSHAN, Foroozan Sarah , WANG, Janet , KELLAM, Mark
IPC分类号： H01L29/02
CPC分类号： H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1658
摘要： A resistive switching device comprises a bottom electrode (115), a switching layer (130) disposed over the bottom electrode (115), and a electrode (150) disposed over the switching layer (130). The top electrode (150) comprises an alloy of a memory metal and an alloying element. The top electrode (150) provides a source of the memory metal. The memory metal is configured to change a state of the switching layer (130).
摘要翻译：电阻式开关装置包括底部电极（115），设置在底部电极（115）上方的开关层（130）和设置在开关层（130）上方的电极（150）。顶部电极（150）包括记忆金属和合金元素的合金。顶部电极（150）提供存储金属的源。存储器金属被配置为改变开关层（130）的状态。

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