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1. 发明申请

WO2017151665A1 READ LATENCY REDUCTION IN A MEMORY DEVICE 审中-公开
标题翻译：读取存储设备中的延迟时间
公开(公告)号：WO2017151665A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/020021
申请日：2017-02-28
申请人： ADESTO TECHNOLOGIES CORPORATION
发明人： INTRATER, Gideon , PEDERSEN, Bard , NAVEH, Ishai
IPC分类号： G11C7/06 , G11C7/10 , G11C7/22 , G11C8/06
CPC分类号： G11C8/06 , G11C5/066 , G11C7/062 , G11C7/103 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C29/021 , G11C29/028 , G11C2029/0409 , G11C2029/5006
摘要： A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.
摘要翻译：存储器件可以包括：具有排列为数据线的存储单元的存储器阵列; 接口，其从起始字节的地址以连续寻址的顺序接收请求字节数据的读命令; 第一缓冲器，其存储来自所述存储器阵列的包括所述起始字节的第一数据线; 第二缓冲器，其存储来自所述存储器阵列的第二数据线，所述第二数据线相对于所述第一数据线被连续寻址; 输出电路，被配置为访问来自缓冲器的数据，并且从起始字节顺序地输出每个字节通过第一数据线的最高寻址字节，并且每个字节从第二数据线的最低寻址字节开始直到所请求的数据字节具有已输出; 以及一个数据选通驱动器，用于为接口上的数据选通器输出的每个字节的数据输出时钟。

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