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    • 84. 发明申请
    • APPARATUS FOR MEASURING MINORITY CARRIER LIFETIMES IN SEMICONDUCTOR MATERIALS
    • 用于测量半导体材料中少数载流子寿命的装置
    • WO9912045A3
    • 1999-05-27
    • PCT/US9818132
    • 1998-09-02
    • MIDWEST RESEARCH INST
    • AHRENKIEL RICHARD K
    • G01N27/00G01R31/265G01R31/28H01L21/66G01R31/26
    • G01R31/2656G01R31/2831H01L22/14H01L2924/0002H01L2924/00
    • An apparatus (30) for determining the minority carrier lifetime of a semiconductor sample (32) includes a positioner for moving the sample relative to a coil (44). The coil (44) is connected to a bridge circuit (42) such that the impedance of one arm of the bridge circuit (42) is varied as sample is positioned relative to the coil (44). The sample (32) is positioned relative to the coil (44) such that any change in the photoconductance of the sample (32) created by illumination of the sample (32) creates a linearly related change in the input impedance of the bridge circuit (42). In addition, the apparatus (30) is calibrated to work at a fixed frequency so that the apparatus (30) maintains a consistently high sensitivity and high linearly for samples of different sizes, shapes, and material properties. When a light source (34) illuminates the sample (32), the impedance of the bridge circuit (42) is altered as excess carriers are generated in the sample (32), thereby producing a measurable signal indicative of the minority carrier lifetimes or recombination rates of the sample (32).
    • 用于确定半导体样品(32)的少数载流子寿命的设备(30)包括用于相对于线圈(44)移动样品的定位器。 线圈(44)连接到桥接电路(42),使得桥接电路(42)的一个臂的阻抗随着样本相对于线圈(44)的定位而变化。 样品(32)相对于线圈(44)定位,使得由样品(32)的照射产生的样品(32)的光电导中的任何变化产生桥电路的输入阻抗的线性相关变化 42)。 此外,设备(30)被校准以在固定频率下工作,使得设备(30)对于不同尺寸,形状和材料特性的样品保持一致的高灵敏度和高线性。 当光源(34)照射样品(32)时,桥式电路(42)的阻抗随着样品(32)中产生过量载流子而改变,由此产生指示少数载流子寿命或重组的可测量信号 样本的比率(32)。
    • 85. 发明申请
    • APPARATUS FOR MEASURING MINORITY CARRIER LIFETIMES IN SEMICONDUCTOR MATERIALS
    • 用于测量半导体材料中少数载体寿命的装置
    • WO99012045A2
    • 1999-03-11
    • PCT/US1998/018132
    • 1998-09-02
    • G01N27/00G01R31/265G01R31/28H01L21/66G01R
    • G01R31/2656G01R31/2831H01L22/14H01L2924/0002H01L2924/00
    • An apparatus (30) for determining the minority carrier lifetime of a semiconductor sample (32) includes a positioner for moving the sample relative to a coil (44). The coil (44) is connected to a bridge circuit (42) such that the impedance of one arm of the bridge circuit (42) is varied as sample is positioned relative to the coil (44). The sample (32) is positioned relative to the coil (44) such that any change in the photoconductance of the sample (32) created by illumination of the sample (32) creates a linearly related change in the input impedance of the bridge circuit (42). In addition, the apparatus (30) is calibrated to work at a fixed frequency so that the apparatus (30) maintains a consistently high sensitivity and high linearly for samples of different sizes, shapes, and material properties. When a light source (34) illuminates the sample (32), the impedance of the bridge circuit (42) is altered as excess carriers are generated in the sample (32), thereby producing a measurable signal indicative of the minority carrier lifetimes or recombination rates of the sample (32).
    • 用于确定半导体样品(32)的少数载流子寿命的装置(30)包括用于相对于线圈(44)移动样品的定位器。 线圈(44)连接到桥接电路(42),使得当样品相对于线圈(44)定位时,桥接电路(42)的一个臂的阻抗是变化的。 样品(32)相对于线圈(44)定位,使得通过样品(32)的照射产生的样品(32)的光电导的任何变化产生桥接电路的输入阻抗的线性相关变化( 42)。 此外,设备(30)被校准为以固定频率工作,使得设备(30)对于不同尺寸,形状和材料性质的样品保持一致的高灵敏度和高线性。 当光源(34)照亮样品(32)时,桥接电路(42)的阻抗随着在样品(32)中产生过量载体而改变,从而产生指示少数载流子寿命或重组的可测量信号 样品率(32)。
    • 86. 发明申请
    • PROBE ASSEMBLY AND METHOD FOR SWITCHABLE MULTI-DUT TESTING OF INTEGRATED CIRCUIT WAFERS
    • 集成电路的可切换多点测试的探头组件和方法
    • WO98047010A1
    • 1998-10-22
    • PCT/US1998/007930
    • 1998-04-16
    • G01R1/073G01R31/28G01R31/02
    • G01R31/2831G01R1/07357
    • A system used to test an integrated circuit (20) on a semiconductor wafer has a support (11) for a plurality of probe needles (14) electrically coupled to the test system wherein the probe needles achieve low contact resistance with low contact force without substantially scrubbing the contact pads (62) of the integrated circuit under test. Each probe needle is curved (14A) in such a manner so as to cause the probe needles to flex in response to compression during mechanical movement of the wafer that further causes the tip of each probe needle to rock without appreciable sliding on the surface of the contact pads of the integrated circuit. The rocking motion of the probe needles result in lateral displacement of oxide on the surface of the contact pads thereby improving electrical contact between the probe needles and the contact pads of the integrated circuit under test.
    • 用于测试半导体晶片上的集成电路(20)的系统具有用于电耦合到测试系统的多个探针(14)的支撑件(11),其中探针具有低接触力而实现低接触力而基本上不 擦洗被测集成电路的接触焊盘(62)。 每个探针是以这样一种方式弯曲的(14A),以便在晶片的机械运动期间响应于压缩而使探针弯曲,这进一步导致每个探针的尖端摇动,而不会在 集成电路的接触焊盘。 探针的摇摆运动导致接触垫表面上的氧化物的横向位移,从而改善探针与被测集成电路的接触垫之间的电接触。
    • 88. 发明申请
    • ALIGNMENT OF WAFER TEST PROBES
    • 波形测试探针对齐
    • WO1992008144A1
    • 1992-05-14
    • PCT/US1991001366
    • 1991-02-27
    • INTERNATIONAL BUSINESS MACHINES CORPORATION
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONBULLARD, Stuart, HowardGASCHKE, Paul, MatthewHERRING, Dean, FrederickHERZ, Andrew, AlfredLAFORCE, Mark, RaymondMENDELSON, Jay, JeffreySTEPHENSON, Mark, Karl
    • G01R31/26
    • G01R1/07314G01R31/2831
    • A method and apparatus for aligning an array of test probes with positions on a semiconductor wafer uses a positioning device having a reference pattern. The positionning device is attached to a substrate transport device. A first location of the positioning device is located under fixed optics. A second location of the positioning device is located under the probe array which corresponds to a predetermined test probe. Both of these steps are accomplished from the operational side of the test probes. The reference pattern of the positioning device and the semiconductor wafer have predetermined spatial relationships with the transport device. Necessary transport device translation for testing can then be calculated using the first and second locations of the reference pattern of the positioning device. In one embodiment the positioning device is an alignment substrate mounted in the test substrate position. Selectively conductive patterns on the alignment substrate can be used to determine the position of the predetermined test probe by measuring the continuity of shorted probe pairs as the alignment substrate is translated. In another embodiment of the invention an optics assembly mounted to the wafer chuck directly observes the fixed optics reticle and the predetermined test probe.
    • 将测试探针阵列与半导体晶片上的位置对准的方法和装置使用具有参考图案的定位装置。 定位装置附接到基板输送装置。 定位装置的第一位置位于固定光学器件下。 定位装置的第二位置位于与预定测试探针对应的探针阵列下方。 这两个步骤都是从测试探头的操作侧完成的。 定位装置和半导体晶片的基准图案与输送装置具有预定的空间关系。 然后可以使用定位装置的参考图案的第一和第二位置来计算用于测试的必要的运输装置平移。 在一个实施例中,定位装置是安装在测试基板位置的对准基板。 对准基板上的选择性导电图案可用于通过在对准基板平移时测量短路探头对的连续性来确定预定测试探针的位置。 在本发明的另一个实施例中,安装到晶片卡盘的光学组件直接观察固定光学掩模版和预定的测试探针。
    • 89. 发明申请
    • 結晶欠陥評価方法
    • 晶体缺陷评估方法
    • WO2018047590A1
    • 2018-03-15
    • PCT/JP2017/029419
    • 2017-08-16
    • 信越半導体株式会社
    • 斉藤 久之
    • H01L21/66C30B29/06
    • G01R31/2831C30B29/06
    • 本発明は、シリコンウェーハ内に存在する結晶欠陥の分布を評価する結晶欠陥評価方法であって、評価する結晶欠陥のサイズと同じ厚さの酸化膜を前記シリコンウェーハに形成して前記シリコンウェーハのGOI特性を測定し、前記GOI特性が低下した領域では前記酸化膜の厚さと同等のサイズの結晶欠陥が存在していたと見做して、前記GOI特性の測定結果から前記シリコンウェーハ内の評価する結晶欠陥サイズの結晶欠陥分布を求めることを特徴とする結晶欠陥評価方法を提供する。これにより、10nm以下の結晶欠陥サイズであっても、結晶欠陥の分布を求めることができる結晶欠陥評価方法が提供される。
    • 本发明是用于评价存在于硅晶片,该硅晶片的晶体缺陷的分布的晶体缺陷的评价方法具有相同厚度作为晶体缺陷评价的尺寸的氧化物层 通过测量硅晶片的GOI特性形成时,在GOI特性降低区域被视为相媲美的氧化膜的尺寸是本厚度的晶体缺陷,的GOI特性的测量结果 硅晶片中待评估的晶体缺陷尺寸的晶体缺陷分布由硅晶片的晶体缺陷分布确定。 由此,提供即使晶体缺陷尺寸为10nm或更小也能够获得晶体缺陷的分布的晶体缺陷评估方法。