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71. 发明申请

WO2014065876A1 HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL 审中-公开
标题翻译：高性能互连协调协议
公开(公告)号：WO2014065876A1
公开(公告)日：2014-05-01
申请号：PCT/US2013032670
申请日：2013-03-15
申请人： BEERS ROBERT , BLANKENSHIP ROBERT G , SAFRANEK ROBERT J , WILLEY JEFF , MADDOX ROBERT A , SPINK AARON T
发明人： BEERS ROBERT , BLANKENSHIP ROBERT G , SAFRANEK ROBERT J , WILLEY JEFF , MADDOX ROBERT A , SPINK AARON T
IPC分类号： G06F13/42 , G06F13/14
CPC分类号： G06F13/4282 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/22 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined
摘要翻译：对应于特定高速缓存行发送一个相干协议消息。识别涉及特定高速缓存行的潜在冲突，并且向归属代理发送转发请求以识别潜在的冲突。响应于来自归属代理的转发请求可以接收转发响应，并且可以确定对冲突的响应

72. 发明申请

WO2014055443A1 MEMORY SHARING ACROSS DISTRIBUTED NODES 审中-公开
标题翻译：存储器分配的分发节点
公开(公告)号：WO2014055443A1
公开(公告)日：2014-04-10
申请号：PCT/US2013/062718
申请日：2013-09-30
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： LOEWENSTEIN, Paul N. , JOHNSON, John G. , KATHIRGAMAR, Aingaran , RADOVIC, Zoran
IPC分类号： G06F17/30
CPC分类号： G06F9/30065 , G06F9/381 , G06F9/3851 , G06F9/3867 , G06F9/546 , G06F12/0804 , G06F12/082 , G06F12/12 , G06F12/1408 , G06F12/1475 , G06F13/102 , G06F13/362 , G06F13/4068 , G06F15/17331 , G06F15/7889 , G06F17/30324 , G06F17/30442 , G06F17/30483 , G06F17/30495 , G06F17/30498 , G06F17/30501 , G06F17/30519 , G06F17/30578 , G06F17/30595 , G06F17/30867 , G06F21/6209 , H04L69/14 , Y02D10/14 , Y02D10/151 , Y02D10/45
摘要： A method and apparatus are disclosed for enabling nodes in a distributed system to share one or more memory portions. A home node makes a portion of its main memory available for sharing, and one or more sharer nodes mirrors that shared portion of the home node's main memory in its own main memory. To maintain memory coherency, a memory coherence protocol is implemented. Under this protocol, load and store instructions that target the mirrored memory portion of a sharer node are trapped, and store instructions that target the shared memory portion of a home node are trapped. With this protocol, valid data is obtained from the home node and updates are propagated to the home node. Thus, no "dirty" data is transferred between sharer nodes. As a result, the failure of one node will not cause the failure of another node or the failure of the entire system.
摘要翻译：公开了一种用于使分布式系统中的节点共享一个或多个存储器部分的方法和装置。家庭节点使其主存储器的一部分可用于共享，并且一个或多个共享节点在其自己的主存储器中镜像家庭节点的主存储器的共享部分。为了保持内存一致性，实现了内存一致性协议。在该协议下，加载和存储指向共享者节点的镜像存储器部分的指令被捕获，并且存储针对家庭节点的共享存储器部分的存储指令被捕获。使用该协议，从家庭节点获得有效数据，并将更新传播到家庭节点。因此，在共享器节点之间不传输“脏”数据。结果，一个节点的故障不会导致另一个节点的故障或整个系统的故障。

73. 发明申请

WO2014038449A1 メモリ制御装置、携帯端末、メモリ制御プログラムおよびコンピュータ読み取り可能な記録媒体审中-公开
标题翻译：存储器控制设备，移动终端，存储器控制程序和计算机可读记录介质
公开(公告)号：WO2014038449A1
公开(公告)日：2014-03-13
申请号：PCT/JP2013/073016
申请日：2013-08-28
申请人：シャープ株式会社
发明人：朝井　淳毅
IPC分类号： G06F12/00 , G06F13/38
CPC分类号： G09G5/393 , G06F13/385 , G09G2330/022 , G09G2360/08 , Y02D10/14 , Y02D10/151
摘要：　期間制御部（３３）は、判定部（３４）によってｒｐおよびｗｐ間の距離がＲＤＩＳＴ未満であると判定された場合に、ｒｐおよびｗｐ間の距離がＲＤＩＳＴ以上になるまで、次のラインの読み出し動作を一時停止させる制御を行う。
摘要翻译：如果由确定单元（34）确定rp和wp之间的距离小于RDIST，则周期控制单元（33）执行控制，使得用于读出下一行的操作被暂时停止，直到 rp表示wp变得大于或等于RDIST。

74. 发明申请

WO2014022474A1 POWER SAVINGS APPARATUS AND METHOD FOR MEMORY DEVICE USING DELAY LOCKED LOOP 审中-公开
标题翻译：节电装置和使用延迟锁定环路的存储器件的方法
公开(公告)号：WO2014022474A1
公开(公告)日：2014-02-06
申请号：PCT/US2013/052852
申请日：2013-07-31
申请人： SPANSION LLC
发明人： HASAN, Qamrul , ZITLAW, Clifford , ROSNER, Stephan , DUBOIS, Sylvain
IPC分类号： G11C8/00 , G11C5/14
CPC分类号： G06F13/16 , G06F1/3275 , G06F13/4239 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.
摘要翻译：实施例涉及通过同步时钟信号降低高频存储器数据传输的功耗。延迟锁定环（DLL）电路用于产生同步的时钟信号。只要输出同步的时钟信号，DLL电路就会消耗电力。描述了一种省电装置和方法，其中当存储器数据访问有效时，DLL电路通电，而当DLL存储器访问空闲时，DLL电路断电。

75. 发明申请

WO2014015071A2 REDUCING UNWANTED REFLECTIONS IN SOURCE-TERMINATED CHANNELS 审中-公开
标题翻译：减少源终端信道中的未反映的反射
公开(公告)号：WO2014015071A2
公开(公告)日：2014-01-23
申请号：PCT/US2013050945
申请日：2013-07-17
申请人： RAMBUS INC
发明人： OH KYUNG SUK , VENKATESAN PRAVIN KUMAR , FRANS YOHAN USTHAVIA
IPC分类号： H04W88/02
CPC分类号： G06F13/4221 , G06F13/28 , H04L25/0278 , H04L25/0298 , Y02B60/1228 , Y02B60/1235 , Y02D10/14 , Y02D10/151
摘要： A memory controller and/or memory device control termination of a communication link in order to achieve power savings while reducing or eliminating unwanted reflections in the channel. Following transmission of data over the communication channel, termination is left enabled for a programmable time period beginning immediately following completion of the transmission. The time period is sufficiently long to allow the unwanted reflections to be absorbed by the termination. Following the time period, the termination is disabled for power savings.
摘要翻译：存储器控制器和/或存储器设备控制通信链路的终端，以便在减少或消除信道中的不必要的反射的同时实现功率节省。在通过通信信道传输数据之后，在传输完成之后立即开始可编程时间段的终止。该时间段足够长以允许不期望的反射被终端吸收。在该时间段之后，终止功能被禁用以节省电力。

76. 发明申请

WO2014011579A2 HYBRID COMPUTING MODULE 审中-公开
标题翻译：混合计算模块
公开(公告)号：WO2014011579A2
公开(公告)日：2014-01-16
申请号：PCT/US2013/049636
申请日：2013-07-09
申请人： DE ROCHEMONT, L., Pierre , KOVACS, Alexander, J.
发明人： DE ROCHEMONT, L., Pierre , KOVACS, Alexander, J.
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/28 , G06F1/324 , G06F3/0619 , G06F3/0625 , G06F3/065 , G06F3/0685 , G06F9/3001 , G06F9/30043 , G06F9/30098 , G06F9/3802 , G06F12/0815 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/1605 , G06F13/1673 , G06F13/1689 , G06F13/24 , G06F13/36 , G06F13/42 , G06F15/80 , G06F2212/1024 , G06F2212/452 , G06F2212/602 , G06F2212/621 , G06F2212/65 , G06F2213/0038 , G11C7/1072 , H01L21/00 , H01L21/76229 , H01L21/84 , H01L25/0652 , H01L25/16 , H01L27/0207 , H01L2924/0002 , H01L2924/14 , H01L2924/3011 , Y02D10/14 , Y02D10/151 , Y10S257/00 , H01L2924/00
摘要： A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die.
摘要翻译：混合片上系统提供安装在半导体载体芯片上的多个存储器和处理器裸片，其包含完全集成的电源管理系统，该电源管理系统以匹配或接近处理器核心时钟的速度切换DC电力速度，从而允许在片外物理内存和处理器芯片之间有效传输数据。

77. 发明申请

WO2014004186A1 ASSIGNING ADDRESSES TO DEVICES ON AN INTERCONNECT 审中-公开
标题翻译：在互连上将设备的地址分配给设备
公开(公告)号：WO2014004186A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/046452
申请日：2013-06-19
申请人： INTEL CORPORATION
发明人： MORRISS, Jeff C. , HARRIMAN, David, J.
IPC分类号： G06F13/14
CPC分类号： G06F13/00 , G06F9/5011 , G06F9/5027 , G06F13/4282 , G06F21/445 , G06F21/73 , G06F2213/0042 , G06F2213/0052 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes an apparatus having a random number generator to generate a random number responsive to a first command from a host controller and a logic to generate a device identifier for the apparatus. The apparatus can provide a reply to the host controller including the random number responsive to an identification request from the host controller corresponding to the device identifier. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有随机数发生器的装置，用于响应于来自主机控制器的第一命令产生随机数，以及生成用于该装置的设备标识符的逻辑。该装置可以向主机控制器提供响应于来自主机控制器的对应于设备标识符的识别请求的随机数的回复。描述和要求保护其他实施例。

78. 发明申请

WO2013180688A1 HIBERNATION BASED ON PAGE SOURCE 审中-公开
标题翻译：基于页面源的HIBERNATION
公开(公告)号：WO2013180688A1
公开(公告)日：2013-12-05
申请号：PCT/US2012/039806
申请日：2012-05-29
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , ATKINSON, Lee, Warren
发明人： ATKINSON, Lee, Warren
IPC分类号： G06F12/00 , G06F9/44
CPC分类号： G06F12/1009 , G06F1/3275 , G06F1/3296 , G06F3/0625 , G06F3/0634 , G06F3/0659 , G06F3/0685 , G06F9/4418 , G06F12/0246 , G06F2212/1028 , G06F2212/202 , G06F2212/2022 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： Example embodiments disclosed herein relate to hibernation. A device includes a non-volatile memory including a solid state memory and a volatile memory. The volatile memory includes a plurality of pages. One or more of the pages are caused to be stored to non-volatile memory based on whether the respective pages are sourced from the solid state memory.
摘要翻译：本文公开的示例实施例涉及休眠。一种设备包括包括固态存储器和易失性存储器的非易失性存储器。易失性存储器包括多个页面。基于各个页面是否来自固态存储器，使得一个或多个页面被存储到非易失性存储器。

79. 发明申请

WO2013176953A1 PROVIDING A CONSOLIDATED SIDEBAND COMMUNICATION CHANNEL BETWEEN DEVICES 审中-公开
标题翻译：在设备之间提供统一的双边通信通道
公开(公告)号：WO2013176953A1
公开(公告)日：2013-11-28
申请号：PCT/US2013/041317
申请日：2013-05-16
申请人： INTEL CORPORATION
发明人： HARRIMAN, David J. , WAGH, Mahesh , GOUGH, Robert E. , JAUSSI, James E.
IPC分类号： H04L29/08 , H04B7/24
CPC分类号： G06F13/4027 , G06F1/3203 , G06F13/20 , G06F13/4295 , G06N99/005 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有事务层和链路层的协议栈。另外，第一物理（PHY）单元被耦合到协议栈，以经由物理链路提供处理器和耦合到处理器的设备之间的通信，其中第一PHY单元是低功率通信协议，并且包括第一物理单位电路。反过来，第二PHY单元被耦合到协议栈，以经由耦合在与物理链路分离的多核处理器和设备之间的边带信道来提供处理器和设备之间的通信，其中第二PHY单元包括第二物理单元电路。描述和要求保护其他实施例。

80. 发明申请

WO2013171537A1 A SYSTEM OF DATA HANDLING BASED ON PERIODIC INTERRUPTIONS TO ELECTRICITY SUPPLY 审中-公开
标题翻译：基于定期中断电力供应的数据处理系统
公开(公告)号：WO2013171537A1
公开(公告)日：2013-11-21
申请号：PCT/IB2012/052378
申请日：2012-05-13
申请人： KURUPPU, Indrajith
发明人： KURUPPU, Indrajith
IPC分类号： G06F13/42
CPC分类号： G06F13/24 , G06F1/26 , G06F13/4286 , Y02D10/14 , Y02D10/151
摘要： An approach to data handling based upon the temporal extents of the interruptions to supply of electricity to selected components is provided. At present, digital electronics and computing is primarily based on the binary system, with fixed time duration in and between the two electricity states in components. Considering the limitations posed, the present innovation employs instruments that utilise the no electricity temporal extents in the selected components, or parts thereof, in the data handling system (100) as a basis for reasoning over plurality of information, simultaneously. The use of dynamic durations in electricity states, including 'no electricity signal' states, accompanied by the punctuations that adopt dynamically determined temporal and electrical characteristics for data handling, in a scalable manner that is task effective and energy saving is disclosed.
摘要翻译：提供了一种基于向所选部件供电的中断的时间范围的数据处理方法。目前，数字电子和计算主要是基于二进制系统，其中组件中两个电状态之间和之间具有固定的持续时间。考虑到所构成的限制，本发明使用在数据处理系统（100）中选择的部件或其部分中的无电时间范围作为推断多个信息的基础的仪器。电力状态中使用动态持续时间，包括“无电信号”状态，伴随着采用动态确定的用于数据处理的时间和电气特性的标点符合可扩展的方式，其中任务有效和节能被公开。

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