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71. 发明申请

WO2013147938A1 SELECTED WORD LINE DEPENDENT PROGRAMMING VOLTAGE 审中-公开
标题翻译：所选字线相关编程电压
公开(公告)号：WO2013147938A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/066614
申请日：2012-11-27
申请人： SANDISK TECHNOLOGIES, INC. , CHEN, Wenzhou , LIANG, Guirong , GU, Lanlan , BO, Lei
发明人： CHEN, Wenzhou , LIANG, Guirong , GU, Lanlan , BO, Lei
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C29/02
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The duration of a programming pulse may depend on the word line that is selected for programming. This could be a physical characteristic of the word line or its location on a NAND string. As one example, a shorter pulse width may be used for the programming signal when programming edge word lines.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线。应用所选字线相关程序条件可能会减少或消除程序干扰。编程脉冲的持续时间可能取决于为编程选择的字线。这可能是字线的物理特征或其在NAND串上的位置。作为一个示例，编程边缘字线时可以使用较短的脉冲宽度用于编程信号。

72. 发明申请

WO2013126109A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：WO2013126109A1
公开(公告)日：2013-08-29
申请号：PCT/US2012/066909
申请日：2012-11-28
申请人： SANDISK TECHNOLOGIES, INC. , OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
发明人： OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
IPC分类号： G11C29/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

73. 发明申请

WO2013096638A1 AUTO CONFIGURABLE TRANSFER AND MANAGEMENT SYSTEM 审中-公开
标题翻译：自动配置传输和管理系统
公开(公告)号：WO2013096638A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/070982
申请日：2012-12-20
申请人： PINK ZULU LABS, INC. , HASHIMOTO, Kaz
发明人： HASHIMOTO, Kaz
IPC分类号： H04W76/02 , H04W84/18 , H04N1/00 , H04W4/00
CPC分类号： G06F17/30265 , H04L67/1095 , H04N1/00137 , H04N1/00167 , H04N2201/3278 , H04W4/80 , H04W84/18
摘要： The technology described herein is directed to a system that quickly and efficiently transmits photographs from a camera to one or more computing devices. The link for such a transmission is easily and automatically configured. Once the photographs are stored in the one or more computing devices, they can be submitted to a photograph management system that facilitates distribution of the photographs as well as collaboration with other individuals or autonomous agents for editing and re-editing of photographs.
摘要翻译：本文描述的技术涉及一种快速有效地将照相机从照相机传输到一个或多个计算设备的系统。用于这种传输的链接是容易且自动配置的。一旦照片存储在一个或多个计算设备中，它们可以被提交给照片管理系统，其便于照片的分发以及与其他个人或自主代理的协作以编辑和重新编辑照片。

74. 发明申请

WO2013095831A1 ERASE OPERATION WITH CONTROLLED SELECT GATE VOLTAGE FOR 3D NON-VOLATILE MEMORY 审中-公开
标题翻译：用于3D非易失性存储器的控制选择栅极电压的擦除操作
公开(公告)号：WO2013095831A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/065739
申请日：2012-11-19
申请人： SANDISK TECHNOLOGIES, INC. , LI, Haibo , COSTA, Xiying , ZHANG, Chenfeng
发明人： LI, Haibo , COSTA, Xiying , ZHANG, Chenfeng
IPC分类号： G11C16/04 , G11C16/16 , G11C16/34
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/344
摘要： An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line (504, 506, 508). A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage (506) to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration (512) of an erase operation, or at a predetermined or adaptively determined erase-verify iteration (516), such as based on a number of program-erase cycles.
摘要翻译：用于3D堆叠存储器件的擦除处理控制NAND串的漏极侧选择栅极（SGD）和源极选择栅极（SGS）。在一种方法中，驱动SGD和SGS以在选择栅极上提供可预测的漏极到栅极电压，同时将擦除电压施加到位线或源极线（504,506,508）。可以产生在选择栅极处更一致的栅极引起的漏极漏极（GIDL），以对NAND串的体进行充电。此外，可以利用擦除电压（506）来升高选择栅极电压，以避免导致退化的选择栅极两端的漏极 - 栅极电压过大。选择栅极电压的升高可以从擦除操作的第一擦除验证迭代（512）开始，或者以预定或自适应确定的擦除验证迭代（516）开始，诸如基于编程擦除的次数周期。

75. 发明申请

WO2013078069A1 3D NON-VOLATILE MEMORY WITH METAL SILICIDE INTERCONNECT 审中-公开
标题翻译：具有金属硅化物互连的3D非易失性存储器
公开(公告)号：WO2013078069A1
公开(公告)日：2013-05-30
申请号：PCT/US2012/065375
申请日：2012-11-15
申请人： SANDISK TECHNOLOGIES, INC. , HIGASHITANI, Masaaki , RABKIN, Peter
发明人： HIGASHITANI, Masaaki , RABKIN, Peter
IPC分类号： H01L27/115 , H01L23/532
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/06 , H01L23/53209 , H01L27/11519 , H01L27/11531 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： A stacked non-volatile memory cell array include cell areas (CA3,4) with rows of vertical columns of NAND cells, and an interconnect area (IA1), e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect (I1, I2) extending between insulation-filled slits (S5, S6, S7), and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.
摘要翻译：堆叠的非易失性存储单元阵列包括具有NAND单元的垂直列行的单元区域（CA3,4），以及例如阵列中途并且延伸阵列的长度的互连区域（IA1）。互连区域包括在绝缘填充的狭缝（S5，S6，S7）之间延伸的至少一个金属硅化物互连（I1，I2），并且不包括NAND单元的垂直列。金属硅化物互连可以将电力和控制信号从堆叠下方传递到堆叠之上。金属硅化物互连也可以形成在衬底的周边区域中。接触结构可以从互连的梯形部分延伸到堆叠之上的至少一个上金属层，以完成从堆叠下方的电路到上金属层的导电路径。可以在阵列的平面中提供子阵列，而不需要字线连接和子阵列之间的传输区域。

76. 发明申请

WO2013028721A1 READ COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF NON-VOLATILE STORAGE 审中-公开
标题翻译：阅读对非易失性存储部分编程块的补偿
公开(公告)号：WO2013028721A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/051797
申请日：2012-08-22
申请人： SANDISK TECHNOLOGIES, INC. , LEE, Dana , OOWADA, Ken
发明人： LEE, Dana , OOWADA, Ken
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3427 , G11C11/5642
摘要： Read compensation for partially programmed blocks of non-volatile storage is provided. In partially programmed blocks, the threshold voltage distributions may be shifted down relative to their final positions. Upon receiving a request to read a page that is stored in a block, a determination may be made whether the block is partially programmed. If so, then a suitable compensation may be made when reading the requested page. This compensation may compensate for the non-volatile storage elements (or pages) in the block that have not yet been programmed. The amount of compensation may be based on the amount of interference that would be caused to the requested page by later programming of the other pages. The compensation may compensate for shifts in threshold voltage distributions of the requested page that would occur from later programming of other pages.
摘要翻译：提供了部分编程的非易失性存储块的读取补偿。在部分编程的块中，阈值电压分布可以相对于其最终位置向下移动。在接收到读取存储在块中的页面的请求时，可以确定块是否被部分编程。如果是这样，那么在阅读请求的页面时可以做出适当的补偿。该补偿可以补偿块中尚未编程的非易失性存储元件（或页）。赔偿金额可以基于通过稍后对其他页面进行编程而对所请求的页面造成的干扰量。该补偿可以补偿所请求页面的阈值电压分布的变化，该偏移将从其他页面的后续编程发生。

77. 发明申请

WO2013022642A1 SYSTEM FOR ENHANCING VIDEO FROM A MOBILE CAMERA 审中-公开
标题翻译：从移动摄像机增强视频的系统
公开(公告)号：WO2013022642A1
公开(公告)日：2013-02-14
申请号：PCT/US2012/048872
申请日：2012-07-30
申请人： SPORTVISION, INC. , MILNES, Kenneth, A. , HONEY, Stanley, K. , MCGUFFIN, James, O. , CAVALLARO, Richard, H. , BORTON, John, R. , PENDELTON, Rand
发明人： MILNES, Kenneth, A. , HONEY, Stanley, K. , MCGUFFIN, James, O. , CAVALLARO, Richard, H. , BORTON, John, R. , PENDELTON, Rand
IPC分类号： H04N5/272 , H04N7/18
CPC分类号： H04N5/272 , G01C21/203 , G01S19/49 , G01S19/53 , H04N7/185
摘要： A system for enhancing video can insert graphics, in perspective, into the video where the positions of the graphics are dependent on sensor measurements of the locations and/or attitudes of objects and the movable camera capturing the video.
摘要翻译：用于增强视频的系统可以将透视图中的图形插入视频中，其中图形的位置取决于物体的位置和/或态度的传感器测量以及捕获视频的可移动摄像机。

78. 发明申请

WO2013019713A1 MEMORY DIE SELF-DISABLE IF PROGRAMMABLE ELEMENT IS NOT TRUSTED 审中-公开
标题翻译：如果可编程元件未被触发，则存储器自动禁止
公开(公告)号：WO2013019713A1
公开(公告)日：2013-02-07
申请号：PCT/US2012/048818
申请日：2012-07-30
申请人： SANDISK TECHNOLOGIES, INC. , TU, Loc , HOOK, Charles, Moana , THEIN, Nyi, Nyi
发明人： TU, Loc , HOOK, Charles, Moana , THEIN, Nyi, Nyi
IPC分类号： G11C29/00
CPC分类号： G11C29/832 , Y10T29/49004
摘要： Techniques are disclosed herein for automatically self-disabling a memory die in the event that a programmable element on the memory die for indicating whether the memory die is defective cannot be trusted. Memory die are provided with chip enable circuitry to allow particular memory die to be disabled. If the programmable element can be trusted, the state of the programmable element is provided to the chip enable circuitry to enable/disable the memory die based on the state. However, if the programmable element cannot be trusted, then the chip enable circuitry may automatically disable the memory die. This provides a greater yield for multi-chip memory packages because packages having memory die with a programmable element that cannot be trusted can still be used.
摘要翻译：在本文中公开了在存储器管芯上用于指示存储器管芯是否有缺陷的可编程元件不能被信任的情况下，自动自身禁用存储器管芯的技术。存储器管芯具有芯片使能电路，以允许禁止特定存储器管芯。如果可编程元件可被信任，则可编程元件的状态被提供给芯片使能电路，以基于该状态启用/禁用存储器管芯。然而，如果可编程元件不能被信任，则芯片使能电路可以自动地禁用存储器管芯。这为多芯片存储器封装提供了更大的收益，因为仍然可以使用具有不可信任的可编程元件的存储器管芯的封装。

79. 发明申请

WO2012134842A1 REDUCING NEIGHBOR READ DISTURB 审中-公开
标题翻译：减少邻居阅读障碍
公开(公告)号：WO2012134842A1
公开(公告)日：2012-10-04
申请号：PCT/US2012/029553
申请日：2012-03-16
申请人： SANDISK TECHNOLOGIES, INC. , KHANDELWAL, Anubhav , WAN, Jun , LEE, Shih-Chung , LEE, Dana
发明人： KHANDELWAL, Anubhav , WAN, Jun , LEE, Shih-Chung , LEE, Dana
IPC分类号： G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn-2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.
摘要翻译：公开了以减少读取干扰的方式感测非易失性存储设备的方法和设备。技术用于减少作为所选存储单元的邻居的存储器单元的读取干扰。例如，在NAND串上，当前正在读取的所选存储单元旁边的存储器单元可能受益。在一个实施例中，当读取选定字线WLn上的存储单元时，Vread + Delta被施加到WLn + 2和WLn-2。将Vread + Delta应用于第二相邻字线可以减少对相邻字线WLn + 1上的存储器单元的读取干扰。

80. 发明申请

WO2012087410A1 ALTERNATE BIT LINE BIAS DURING PROGRAMMING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING IN MEMORY 审中-公开
标题翻译：编程期间的替代位线偏移，以减少存储器中的通道到浮动栅极耦合
公开(公告)号：WO2012087410A1
公开(公告)日：2012-06-28
申请号：PCT/US2011/056144
申请日：2011-10-13
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , LUTZE, Jeffrey, W.
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W.
IPC分类号： G11C16/24 , G11C16/34
CPC分类号： G11C16/24 , G11C16/3418 , G11C16/3436
摘要： In a non-volatile storage system, capacitive coupling effects are reduced by reducing the probability that adjacent storage elements reach the lockout condition at close to the same program pulse. A slow down measure such as an elevated bit line voltage is applied to the storage elements of a word line which are associated with odd-numbered bit lines, but not to the storage elements associated with even-numbered bit lines. The elevated bit line voltage is applied over a range of program pulses, then stepped down to ground over one or more program pulses. The range of programming pulses over which the slow down measure is applied, can be fixed or determined adaptively. A program pulse increment can be dropped, then increased, when the bit line voltage is stepped down. Storage elements which are programmed to a highest target data state can be excluded from the slow down measure.
摘要翻译：在非易失性存储系统中，通过减少相邻存储元件在接近相同的编程脉冲时达到锁定状态的可能性来降低电容耦合效应。诸如提升的位线电压之类的减速措施被施加到与奇数位线相关联的字线的存储元件，而不是与与偶数位线相关联的存储元件。升高的位线电压施加在编程脉冲的范围上，然后通过一个或多个编程脉冲降压到地。施加减速措施的编程脉冲的范围可以自适应地固定或确定。当位线电压降低时，程序脉冲增量可以下降，然后增加。被编程为最高目标数据状态的存储元件可以从减速测量中排除。

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