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1. 发明申请

WO2014046887A1 BLOCK AND PAGE LEVEL BAD BIT LINE AND BITS SCREENING METHOD FOR NON-VOLATILE MEMORY 审中-公开
标题翻译： BLOCK AND PAGE LEVEL BAD BIT LINE AND BITS SCREENING METHOD FOR NON-VOLATILY MEMORY
公开(公告)号：WO2014046887A1
公开(公告)日：2014-03-27
申请号：PCT/US2013/058470
申请日：2013-09-06
申请人： SANDISK TECHNOLOGIES, INC. , WAN, Jun , LEI, Bo , PAN, Feng , SUN, Yongke
发明人： WAN, Jun , LEI, Bo , PAN, Feng , SUN, Yongke
IPC分类号： G11C29/02 , G11C29/44 , G11C7/10 , G11C11/56 , G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/349 , G11C7/1006 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/10 , G11C16/24 , G11C16/3409 , G11C16/3413 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C16/3445 , G11C16/345 , G11C16/3459 , G11C29/025 , G11C29/44 , G11C2029/1204
摘要： A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.
摘要翻译：编程过程评估块的NAND串以检测有缺陷的NAND串，例如具有缺陷存储元件的NAND串。可以存储识别有缺陷的NAND串的状态位。要写入NAND串的原始数据被修改，使得不会发生有缺陷的NAND串的编程。例如，将要编程到较高数据状态的有缺陷的NAND串中的存储元件的一些写入数据修改（例如翻转），使得不需要存储元件的编程。随后，当执行读取操作时，例如通过使用纠错码解码，将翻转的位翻转回其原始值。在擦除处理中，进行有缺陷的NAND串的计数并用于调整验证测试的通过条件。

2. 发明申请

WO2012134842A1 REDUCING NEIGHBOR READ DISTURB 审中-公开
标题翻译：减少邻居阅读障碍
公开(公告)号：WO2012134842A1
公开(公告)日：2012-10-04
申请号：PCT/US2012/029553
申请日：2012-03-16
申请人： SANDISK TECHNOLOGIES, INC. , KHANDELWAL, Anubhav , WAN, Jun , LEE, Shih-Chung , LEE, Dana
发明人： KHANDELWAL, Anubhav , WAN, Jun , LEE, Shih-Chung , LEE, Dana
IPC分类号： G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn-2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.
摘要翻译：公开了以减少读取干扰的方式感测非易失性存储设备的方法和设备。技术用于减少作为所选存储单元的邻居的存储器单元的读取干扰。例如，在NAND串上，当前正在读取的所选存储单元旁边的存储器单元可能受益。在一个实施例中，当读取选定字线WLn上的存储单元时，Vread + Delta被施加到WLn + 2和WLn-2。将Vread + Delta应用于第二相邻字线可以减少对相邻字线WLn + 1上的存储器单元的读取干扰。

3. 发明申请

WO2011008367A1 DYNAMICALLY ADJUSTABLE ERASE AND PROGRAM LEVELS FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的动态可调删除和程序级别
公开(公告)号：WO2011008367A1
公开(公告)日：2011-01-20
申请号：PCT/US2010/037845
申请日：2010-06-08
申请人： SANDISK CORPORATION , DONG, Yingda , WAN, Jun
发明人： DONG, Yingda , WAN, Jun
IPC分类号： G11C16/16 , G11C16/34
CPC分类号： G11C16/344 , G11C16/16
摘要： Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, (1) or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit (2), the erase-verify level is increased (3). As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program- verify levels can also be increased in concert with changes in the erase-verify level. The one or more program- verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided. (1) =1124,1132), (2) = 1136). (3)1138)
摘要翻译：通过自适应地调整擦除验证级别和程序验证级别来降低非易失性存储元件的降级。确定完成擦除操作所需的擦除脉冲数（1）或最高擦除脉冲幅度。当数字或幅度达到极限（2）时，擦除验证电平增加（3）。随着擦除验证电平的增加，所需擦除脉冲的数量减少，因为擦除操作可以更容易地完成。从而避免了退化的加速增加。一个或多个程序验证电平也可以随着擦除验证电平的变化而增加。一个或多个程序验证电平可以增加与擦除验证电平相同的增量，以在擦除状态和编程状态之间维持恒定的阈值电压窗口，或者通过不同的增量。提供了具有二进制或多级存储元素的实现。（1）= 1124,1132）（2）= 1136）。（3）1138）

4. 发明申请

WO2010000089A1 STAT3 AND TYK2 AS DRUG TARGETS FOR NEURODEGENERATIVE DISEASES 审中-公开
标题翻译： STAT3和TYK2作为治疗神经病变的药物目标
公开(公告)号：WO2010000089A1
公开(公告)日：2010-01-07
申请号：PCT/CN2008/001245
申请日：2008-06-30
申请人： BIOTECHNOLOGY RESEARCH CORPORATION LIMITED , YUK-YU-IP, Nancy , WU, Zhenguo , WANG, Jerry Hsueh-Ching , FU, Kit Yu , WAN, Jun
发明人： YUK-YU-IP, Nancy , WU, Zhenguo , WANG, Jerry Hsueh-Ching , FU, Kit Yu , WAN, Jun
IPC分类号： G01N33/566 , G01N33/50 , A61P25/28
CPC分类号： G01N33/6896 , G01N33/6872 , G01N2333/9121 , G01N2500/04 , G01N2500/10 , G01N2500/20 , Y10T436/143333
摘要： The invention provides Stat3 and Tyk2 targets that have importance for diagnosis of neurodegenerative diseases such as Alzheimer's disease. Stat3 and Tyk2 are also important as targets for drug development for neurodegenerative diseases.
摘要翻译：本发明提供对诊断神经变性疾病如阿尔茨海默氏病具有重要意义的Stat3和Tyk2靶标。 Stat3和Tyk2也作为神经退行性疾病药物开发的目标是重要的。

5. 发明申请

WO2007067447A1 REDUCING READ DISTURB FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：减少读取干扰非易失性存储
公开(公告)号：WO2007067447A1
公开(公告)日：2007-06-14
申请号：PCT/US2006/046126
申请日：2006-11-30
申请人： SANDISK CORPORATION , FONG, Yupin , WAN, Jun , LUTZE, Jeffrey
发明人： FONG, Yupin , WAN, Jun , LUTZE, Jeffrey
IPC分类号： G11C16/04 , G11C16/34
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C2211/5642
摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.
摘要翻译：公开了一种用于减少或去除非易失性存储装置中的读取干扰形式的系统。一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

6. 发明申请

WO2006124525A1 SELECTIVE APPLICATION OF PROGRAM INHIBIT SCHEMES IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中选择性应用程序抑制方案
公开(公告)号：WO2006124525A1
公开(公告)日：2006-11-23
申请号：PCT/US2006/018278
申请日：2006-05-11
申请人： SANDISK CORPORATION , WAN, Jun , LUTZE, Jeffrey , HIGASHITANI, Masaaki , HEMINK, Gerrit, Jan , OOWADA, Ken , CHEN, Jian , GONGWER, Geoffrey, S.
发明人： WAN, Jun , LUTZE, Jeffrey , HIGASHITANI, Masaaki , HEMINK, Gerrit, Jan , OOWADA, Ken , CHEN, Jian , GONGWER, Geoffrey, S.
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择编程抑制方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

7. 发明申请

WO2014039164A1 ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：芯片动态读取级别扫描和错误检测非易失性存储
公开(公告)号：WO2014039164A1
公开(公告)日：2014-03-13
申请号：PCT/US2013/049733
申请日：2013-07-09
申请人： SANDISK TECHNOLOGIES, INC. , LEE, Dana , CHEN, Wenzhou , DUTTA, Deepanshu , CHEN, Yi-chieh , ZHOU, Zhenming , WAN, Jun
发明人： LEE, Dana , CHEN, Wenzhou , DUTTA, Deepanshu , CHEN, Yi-chieh , ZHOU, Zhenming , WAN, Jun
IPC分类号： G11C11/56 , G11C16/34 , G11C16/26 , G06F11/00 , G11C29/02
CPC分类号： G06F11/1068 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/349 , G11C29/028 , G11C29/52
摘要： Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels (1102, 1104). The results are compared to determine a count how many memory cells showed a different result between the two reads (1106). If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads (1110). If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads (1112, 1114). A programming operation may be performed based on the data stored in the set of data latches (1116).
摘要翻译：公开了用于有效地编程非易失性存储器的技术。可以将第二页数据有效地编程到已经存储第一页的存储器单元中。数据可以从单个位单元有效地传送到多位单元。使用至少两个不同的读取级别读取存储器单元（1102,1104）。将结果进行比较以确定计数在两次读取之间有多少个存储单元显示不同的结果（1106）。如果计数小于阈值，则来自存储器单元的数据被存储到一组数据锁存器中，而不尝试校正误读（1110）。如果计数不小于阈值，则来自存储器单元的数据被存储到数据锁存器集合中，试图校正误读（1112,1114）。可以基于存储在该组数据锁存器（1116）中的数据来执行编程操作。

8. 发明申请

WO2009054597A1 HAND-HELD TYPE AROMATIC DIFFUSING CAPSULE 审中-公开
标题翻译：手持式芳香弥漫胶囊
公开(公告)号：WO2009054597A1
公开(公告)日：2009-04-30
申请号：PCT/KR2008/003981
申请日：2008-07-07
申请人： KANG, Wan-Jun , RYU, Chi-Hoon
发明人： KANG, Wan-Jun , RYU, Chi-Hoon
IPC分类号： A61L9/12
CPC分类号： A61L9/12
摘要： Disclosed is a hand-held type aromatic capsule including: a fragrance receptacle having an outlet formed in a top portion thereof; a capsule body including a tube-shaped cylinder having fragrance releasing holes formed thereon, and a supporting bar radially formed on an inner wall of the cylinder and formed in a central region thereof with a shaft hole; a cap including a supporting tube vertically formed on a bottom surface within, and being formed in a top surface thereof with a button insertion hole interconnected with the supporting tube; a guide tube has a length long enough to get out of the supporting tube and enter an inside of the cylinder in a state where the cap is assembled to the cylinder; a button including a button body part and a button post part extending from the button body part; an opening/closing part including an opening/ closing shaft capable of passing through the shaft hole, an opening/closing plate assembled to a lower end of the opening/closing shaft, and an opening/closing operating part allowing the opening/closing shaft to move from a closing position where the outlet is closed by the opening/ closing plate to an opening position where the outlet is opened by the opening/closing plate, by a pressing operation of the button; and a pumping part including a piston provided in an area between the guide tube and the cylinder so as to move in a longitudinal direction of the cylinder; and a lower return spring whose both ends are supported by the piston and the supporting bar; and an upper return spring whose both ends are supported by the piston and the bottom surface within the cap.
摘要翻译：公开了一种手持式芳香胶囊，其包括：香味容器，其具有形成在其顶部的出口; 胶囊主体，其具有形成在其上的香味释放孔的管状筒体和径向形成在所述圆筒的内壁上并具有轴孔的中心区域的支撑杆; 帽，其包括垂直形成在其内表面的支撑管，并且在其顶表面中形成有与所述支撑管互连的按钮插入孔; 引导管具有足够长的长度以在盖组装到气缸的状态下离开支撑管并进入气缸的内部; 包括按钮主体部分和从按钮主体部分延伸的按钮后部部分的按钮; 包括能够穿过轴孔的打开/关闭轴的打开/关闭部分，组装到打开/关闭轴的下端的打开/关闭板以及允许打开/关闭轴通过按钮的按压操作，从出口被开闭板关闭的关闭位置移动到通过开闭板打开出口的打开位置; 以及泵送部，其包括设置在所述引导管和所述气缸之间的区域中的活塞，以沿所述气缸的纵向方向移动; 以及下端复位弹簧，其两端由活塞和支撑杆支撑; 以及上端复位弹簧，其两端由活塞和盖内的底面支撑。

9. 发明申请

WO2013138199A1 NON-VOLATILE STORAGE WITH READ PROCESS THAT REDUCES DISTURB 审中-公开
标题翻译：具有读取过程的非易失性存储，减少了干扰
公开(公告)号：WO2013138199A1
公开(公告)日：2013-09-19
申请号：PCT/US2013/029991
申请日：2013-03-08
申请人： SANDISK TECHNOLOGIES, INC. , LEI, Bo , WAN, Jun , PAN, Feng
发明人： LEI, Bo , WAN, Jun , PAN, Feng
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3427
摘要： A apparatus and process for reading data from non-volatile storage includes applying a read compare signal to a selected data memory cell of a NAND string, applying a first set of one or more read pass voltages to unselected data memory cells at both ends of the NAND string and applying a second set of one or more read pass voltages to unselected data memory cells between both ends of the NAND string and on both sides of the selected data memory cell. The second set of one or more read pass voltages are all higher than the first set of one or more read pass voltages.
摘要翻译：用于从非易失性存储器读取数据的装置和处理包括将读取的比较信号应用于NAND串的所选择的数据存储单元，将第一组一个或多个读取通过电压施加到未读选择数据存储单元的两端 NAND串，并且将第二组一个或多个读取通过电压施加到NAND串的两端和所选数据存储单元的两侧之间的未选择的数据存储单元。第一组一个或多个读通道电压都高于一个或多个读通道电压的第一组。

10. 发明申请

WO2011146241A1 ERASE AND PROGRAMMING TECHNIQUES TO REDUCE THE WIDENING OF STATE DISTRIBUTIONS IN NON-VOLATILE MEMORIES 审中-公开
标题翻译：删除和编程技术减少非易失性存储器中状态分布的增加
公开(公告)号：WO2011146241A1
公开(公告)日：2011-11-24
申请号：PCT/US2011/035190
申请日：2011-05-04
申请人： SANDISK CORPORATION , LEI, Bo , LIANG, Guirong , KHANDELWAL, Anubhav , WAN, Jun
发明人： LEI, Bo , LIANG, Guirong , KHANDELWAL, Anubhav , WAN, Jun
IPC分类号： G11C16/16 , G11C16/34
CPC分类号： G11C16/16 , G11C16/3404
摘要： Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.
摘要翻译：提供了用于存储器件的技术，以通过减少在多个写入/擦除周期之后发生的状态分布的扩大来提高可靠性和耐久性。一组技术使用预处理操作，其中可以包括程序和温和擦除的脉冲序列被施加到一个或多个字线，同时在字线方向，位线方向或两者上施加电压差。另一组技术使用双脉冲或多脉冲程序过程，其中在一对的第一脉冲中使用增加的字线对字线差分。

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