专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

WO2005024907A3 VERTICAL ORGANIC FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：垂直有机场效应晶体管
公开(公告)号：WO2005024907A3
公开(公告)日：2005-09-15
申请号：PCT/US2004027579
申请日：2004-08-24
申请人： UNIV CALIFORNIA , YANG YANG , MA LIPING
发明人： YANG YANG , MA LIPING
IPC分类号： H01L20060101 , H01L29/772 , H01L51/00 , H01L51/05
CPC分类号： H01L51/057 , B82Y10/00 , H01L51/0036 , H01L51/0038 , H01L51/0039 , H01L51/0046 , H01L51/0047 , H01L51/0059 , H01L51/0078 , H01L51/0081 , H01L51/0512 , H01L51/055
摘要： A vertical organic field effect transistor that includes an active cell and a capacitor that share a common source electrode. The active cell includes a semiconductor layer that is sandwiched between a drain electrode and the common source electrode. The capacitor includes a dielectric layer that is sandwiched between a gate electrode and the common source electrode. The common source electrode allows control of electrical current between the source and drain electrodes by controlling the electrical potential that is applied to the gate electrode.
摘要翻译：一种垂直有机场效应晶体管，其包括共用公共源电极的有源电池和电容器。活性电池包括夹在漏电极和公共源电极之间的半导体层。电容器包括夹在栅电极和公共源电极之间的电介质层。公共源电极通过控制施加到栅电极的电位来允许控制源极和漏极之间的电流。

52. 发明申请

WO2005078819A1 METHODS OF FABRICATING VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR ARRANGEMENT IN ARRAYS AND FIELD EFFECT TRANSISTORS AND ARRAYS FORMED THEREBY 审中-公开
标题翻译：制造垂直碳纳米管场效应晶体管的方法，用于阵列中的布置和场效应晶体管及其形成的阵列
公开(公告)号：WO2005078819A1
公开(公告)日：2005-08-25
申请号：PCT/EP2005/050591
申请日：2005-02-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , KOBURGER, Charles, William, III , MITCHELL, Peter , NESBIT, Larry, Alan
发明人： FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , KOBURGER, Charles, William, III , MITCHELL, Peter , NESBIT, Larry, Alan
IPC分类号： H01L51/20
CPC分类号： H01L51/057 , B82Y10/00 , G11C13/025 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/66409 , H01L29/772 , H01L51/0048 , Y10S977/734
摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.
摘要翻译：一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。栅电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。多个器件结构可以被配置为存储器电路或逻辑电路。

53. 发明申请

WO2005076382A1 VERTICAL FIELD EFFECT TRANSISTORS INCORPORATING SEMICONDUCTING NANOTUBES GROWN IN A SPACER-DEFINED PASSAGE 审中-公开
标题翻译：包含半导体纳米管的垂直场效应晶体管
公开(公告)号：WO2005076382A1
公开(公告)日：2005-08-18
申请号：PCT/EP2005/050128
申请日：2005-01-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , MITCHELL, Peter , NESBIT, Larry, Alan
发明人： FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , MITCHELL, Peter , NESBIT, Larry, Alan
IPC分类号： H01L51/30
CPC分类号： H01L27/283 , B82Y10/00 , H01L51/0048 , H01L51/057 , Y10S977/70 , Y10S977/707 , Y10S977/721 , Y10S977/724
摘要： Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.
摘要翻译：具有由至少一个半导体纳米管限定的沟道区的垂直场效应晶体管以及通过使用间隔物定义的沟道的化学气相沉积来制造这种垂直场效应晶体管的方法。每个纳米管通过化学气相沉积来生长，该催化剂垫位于位于间隔物和栅电极之间限定的高纵横比通道的基部处的催化剂垫。每个纳米管在通道中生长，其中垂直取向受限于间隔物的限制。可以在远离通道的口的间隔件的基部中设置间隙。通过间隙流过催化剂垫的反应物参与纳米管生长。

54. 发明申请

WO2004055920A3 ELECTRONIC DEVICES 审中-公开
标题翻译：电子设备
公开(公告)号：WO2004055920A3
公开(公告)日：2004-10-07
申请号：PCT/GB0305435
申请日：2003-12-12
申请人： PLASTIC LOGIC LTD , BROWN THOMAS MEREDITH , SIRRINGHAUS HENNING
发明人： BROWN THOMAS MEREDITH , SIRRINGHAUS HENNING
IPC分类号： H01L21/762 , H01L51/00 , H01L51/05 , H01L51/10 , H01L51/30 , H01L51/40 , H01L51/20
CPC分类号： B05D5/12 , B05D1/322 , B05D3/145 , B82Y10/00 , B82Y30/00 , H01L51/0016 , H01L51/0017 , H01L51/0021 , H01L51/0022 , H01L51/0023 , H01L51/0036 , H01L51/0037 , H01L51/0039 , H01L51/0043 , H01L51/052 , H01L51/0525 , H01L51/0541 , H01L51/0545 , H01L51/057 , H01L51/105 , H01L2251/105 , Y10S977/887
摘要： A method for forming an electronic device in a multilayer structure comprising the steps of: defining a topographic profile in a laterally extending first layer; depositing at least one non-planarizing layer on top of the first layer such that the topographic profile of the surface of the or each non-planarizing layer conforms to that of the laterally extending first layer; and depositing a pattern of at least one additional layer onto the top-most non-planarizing layer, such that the lateral location of the additional layer is defined by the shape of the topographic profile of the non-planarizing layer, and whereby the additional layer is laterally aligned with the topographic profile in the first layer.
摘要翻译：一种用于在多层结构中形成电子器件的方法，包括以下步骤：在横向延伸的第一层中限定形貌轮廓; 在所述第一层的顶部上沉积至少一个非平坦化层，使得所述或每个非平坦化层的表面的形貌轮廓符合所述横向延伸的第一层的表面; 以及将至少一个附加层的图案沉积到最上面的非平坦化层上，使得附加层的横向位置由非平坦化层的形貌构成，并由此附加层与第一层中的形貌轮廓横向对齐。

55. 发明申请

WO2004055919A2 ELECTRONIC DEVICES 审中-公开
标题翻译：电子设备
公开(公告)号：WO2004055919A2
公开(公告)日：2004-07-01
申请号：PCT/GB2003/005430
申请日：2003-12-12
申请人： PLASTIC LOGIC LIMITED , BROWN, Thomas , SIRRINGHAUS, Henning , MACKENZIE, Devin, John
发明人： BROWN, Thomas , SIRRINGHAUS, Henning , MACKENZIE, Devin, John
IPC分类号： H01L51/20
CPC分类号： B05D5/12 , B05D1/322 , B05D3/145 , B82Y10/00 , B82Y30/00 , H01L51/0016 , H01L51/0017 , H01L51/0021 , H01L51/0022 , H01L51/0023 , H01L51/0036 , H01L51/0037 , H01L51/0039 , H01L51/0043 , H01L51/052 , H01L51/0525 , H01L51/0541 , H01L51/0545 , H01L51/057 , H01L51/105 , H01L2251/105 , Y10S977/887
摘要： A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and second regions of the substrate so as to form a first electrode on the first region and a second electrode on the second region, wherein the electrodes are electrically insulated from each other by the third region.
摘要翻译：一种形成具有多层结构的电子器件的方法，包括：对衬底的表面进行压花，以相对于衬底的至少第三区域压下衬底的第一和第二区域; 将溶液中的导电或半导体材料沉积到衬底的第一和第二区域上，以在第一区域上形成第一电极，在第二区域上形成第二电极，其中电极通过第三区域彼此电绝缘。

56. 发明申请

WO2003094237A1 線状素子及びその製造方法审中-公开
标题翻译：线元素和制造线元件的方法
公开(公告)号：WO2003094237A1
公开(公告)日：2003-11-13
申请号：PCT/JP2003/005620
申请日：2003-05-02
申请人：株式会社イデアルスター , 笠間泰彦 , 藤本諭 , 表研次
发明人：笠間泰彦 , 藤本諭 , 表研次
IPC分类号： H01L29/06
CPC分类号： H01L51/057 , B82Y10/00 , H01L27/10873 , H01L27/10897 , H01L27/11 , H01L27/11517 , H01L29/0657 , H01L51/0048 , H01L51/0052
摘要：形状に限定されることなく、柔軟性ないし可撓性を有し、任意の形状の各種装置を作成することが可能な素子及びその製造方法を提供すること。回路素子が長手方向に連続的又は間欠的に形成されていることを特徴とする素子。回路を形成する複数の領域を有する断面が長手方向に連続的又は間欠的に形成されていることを特徴とする素子。
摘要翻译：一种能够制造具有柔性而不受形状限制的任何形状的各种类型的装置的元件以及该元件的制造方法，其特征在于，电路元件沿纵向方向连续地或间断地形成，并且具有形成电路的多个区域沿长度方向连续地或间歇地形成。

57. 发明申请

WO2018103161A1 柔性垂直沟道有机薄膜晶体管及其制作方法审中-公开
公开(公告)号：WO2018103161A1
公开(公告)日：2018-06-14
申请号：PCT/CN2016/113013
申请日：2016-12-29
申请人：武汉华星光电技术有限公司
发明人：卜呈浩 , 胡国仁
IPC分类号： H01L51/50 , H01L51/52 , H01L51/56
CPC分类号： H01L27/3274 , H01L27/3262 , H01L29/7827 , H01L51/0048 , H01L51/0525 , H01L51/0558 , H01L51/057 , H01L51/102 , H01L51/5206
摘要：本发明提供一种柔性垂直沟道有机薄膜晶体管及其制作方法，改变了传统的平面沟道有机薄膜晶体管的构型，使用垂直沟道构型极大的缩短了沟道长度，使得薄膜晶体管可以在较低的驱动电压下获得较大的源漏电流；使用无缺陷、具有高导电性及高透明度的石墨烯材料制备栅极，使得薄膜晶体管的电学性能更好；使用六方氮化硼材料制备栅极绝缘层，与石墨烯材料制备的栅极共同作用，提高了薄膜晶体管的电学性能，并且由于石墨烯材料与六方氮化硼材料均为弯折性能较好的二维原子层结构材料，同时沟道层采用具有柔性的有机半导体材料，使得整个有机薄膜晶体管的弯折性能得到大幅度提高，有利于有机薄膜晶体管在柔性OLED显示屏中的应用。

58. 发明申请

WO2015144865A1 METHOD FOR PRODUCING AN ORGANIC TRANSISTOR AND ORGANIC TRANSISTOR 审中-公开
标题翻译：用于生产有机晶体管和有机晶体管的方法
公开(公告)号：WO2015144865A1
公开(公告)日：2015-10-01
申请号：PCT/EP2015/056674
申请日：2015-03-27
申请人： NOVALED GMBH
发明人： KLEEMANN, Hans , BLOCHWITZ-NIMOTH, Jan , SCHWARTZ, Gregor
IPC分类号： H01L51/05
CPC分类号： H01L51/057 , H01L51/0003 , H01L51/0023 , H01L51/0541 , H01L51/105
摘要： The invention refers to a method for producing an organic transistor, the method comprising steps of providing a first electrode (2) on a substrate (1), generating a source-drain insulator (3) assigned at least partially to the substrate (1) and/or at least partially to the first electrode (2), generating a second electrode (4) assigned to the source-drain insulator (3), depositing an organic semiconducting layer (5) on the first electrode (2), the second electrode (4), and the source-drain insulator (3), generating a gate insulator (6) assigned to the organic semiconducting layer (5), and providing a gate electrode (7) assigned to the gate insulator (6). Further, the invention relates to an organic transistor.
摘要翻译：本发明涉及一种制造有机晶体管的方法，该方法包括以下步骤：在衬底（1）上提供第一电极（2），产生至少部分地分配给衬底（1）的源极 - 漏极绝缘体（3）和/或至少部分地耦合到第一电极（2），产生分配给源极 - 漏极绝缘体（3）的第二电极（4），在第一电极（2）上沉积有机半导体层（5）电极（4）和源极 - 漏极绝缘体（3），产生分配给有机半导体层（5）的栅极绝缘体（6），以及提供分配给栅极绝缘体（6）的栅电极（7）。此外，本发明涉及有机晶体管。

59. 发明申请

WO2014085410A8 AMBIPOLAR VERTICAL FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：环形垂直场效应晶体管
公开(公告)号：WO2014085410A8
公开(公告)日：2014-07-31
申请号：PCT/US2013071919
申请日：2013-11-26
申请人： UNIV FLORIDA
发明人： RINZLER ANDREW GABRIEL , LIU BO , MCCARTHY MITCHELL AUSTIN
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L51/057 , B82Y10/00 , H01L27/092 , H01L27/283 , H01L29/0673 , H01L29/1606 , H01L29/413 , H01L29/7395 , H01L29/775 , H01L51/0039 , H01L51/0047 , H01L51/0048 , H01L51/0566 , H01L51/102 , H01L51/105
摘要： Various examples are provided for ambipolar vertical field effect transistors (VFETs). In one example, among others, an ambipolar VFET includes a gate layer; a source layer that is electrically percolating and perforated; a dielectric layer; a drain layer; and a semiconducting channel layer. The semiconducting channel layer is in contact with at least a portion of the source layer and at least a portion of the dielectric layer and the source layer and the semiconducting channel layer form a gate voltage tunable charge injection barrier. Another example includes an ambipolar vertical field effect transistor including a dielectric surface treatment layer. The semiconducting channel layer is in contact with at least a portion of the source layer and at least a portion of the dielectric surface treatment layer and where the source layer and the semiconducting channel layer form a gate voltage tunable charge injection barrier.
摘要翻译：为双极垂直场效应晶体管（VFET）提供了各种示例。在一个示例中，其中，双极VFET包括栅极层; 电渗透和穿孔的源层; 电介质层; 漏层; 和半导体沟道层。半导体沟道层与源极层的至少一部分接触，并且电介质层和源极层以及半导体沟道层的至少一部分形成栅极电压可调电荷注入势垒。另一个例子包括一个包括电介质表面处理层的双极垂直场效应晶体管。半导体沟道层与源极层的至少一部分和电介质表面处理层的至少一部分接触，并且其中源极层和半导体沟道层形成栅极电压可调电荷注入势垒。

60. 发明申请

WO2013089556A1 A METHOD OF FORMING A DEVICE WITH NANOSTRUCTURES 审中-公开
标题翻译：一种形成具有纳米结构的器件的方法
公开(公告)号：WO2013089556A1
公开(公告)日：2013-06-20
申请号：PCT/MY2012/000186
申请日：2012-06-29
申请人： MIMOS BHD. , TEH, Aun Shih , BIEN, Daniel Chia Sheng , LEE, Hing Wah
发明人： TEH, Aun Shih , BIEN, Daniel Chia Sheng , LEE, Hing Wah
IPC分类号： H01L29/775 , H01L29/06 , H01L29/66 , H01L29/78 , H01L51/00 , H01L51/05 , H01L27/06 , H01L21/8234 , B82Y40/00 , B82Y10/00
CPC分类号： H01L29/0676 , B82Y10/00 , B82Y40/00 , H01L21/823487 , H01L27/0688 , H01L29/66439 , H01L29/775 , H01L29/7827 , H01L51/0048 , H01L51/057
摘要： The present invention generally relates to a method of forming nanotubes or nanowires device in an opening, more particularly the present invention relates to method of forming device structures using random nanotubes or nanowires formations. The device with nanostructrures as formed according to the method described in the present invention comprises first, a substrate (11). Then, at least a conductive layer (21), at least a dielectric layer (22), and at least a catalyst layer (23) deposited on the substrate (11) for structuring the device, wherein the catalyst layer (23) is sandwiched between conductive layers (21) of two devices of the same type. An opening (24) is etched through said layers for, after which a plurality of nanostructures (25) is formed, bridging conductive layers within one of the two devices.
摘要翻译：本发明一般涉及一种在开口中形成纳米管或纳米线装置的方法，更具体地说，本发明涉及使用无规纳米管或纳米线形成形成器件结构的方法。具有根据本发明所述方法形成的纳米结构的器件首先包括衬底（11）。然后，至少导电层（21），至少介电层（22）和沉积在基板（11）上的至少一催化剂层（23），用于构造该器件，其中催化剂层（23）夹在在相同类型的两个装置的导电层（21）之间。通过所述层蚀刻开口（24），之后形成多个纳米结构（25），在两个器件之一内桥接导电层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式