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51. 发明申请

WO2017171821A1 PROGRAMMABLE METALLIZATION CELL WITH ALLOY LAYER 审中-公开
标题翻译：具有合金层的可编程金属化电池
公开(公告)号：WO2017171821A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025437
申请日：2016-03-31
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , BIELEFELD, Jeffery D. , CLARKE, James S. , PILLARISETTY, Ravi , SHAH, Uday
IPC分类号： H01L45/00 , H01L45/02
摘要： An embodiment includes a programmable metallization cell (PMC) memory comprising: a top electrode and a bottom electrode; a metal layer between the top and bottom electrodes; and a solid electrolyte (SE) layer between the metal layer and the bottom electrode; wherein (a) the metal layer includes an alloy of first and second metals, and (b) metal ions from the first metal form a conductive path in the SE layer when the top electrode is positively biased and disband the conductive path when the top electrode is negatively biased. Other embodiments are described herein.
摘要翻译：一个实施例包括一种可编程金属化单元（PMC）存储器，其包括：顶部电极和底部电极; 顶部和底部电极之间的金属层; 和在金属层和底部电极之间的固体电解质（SE）层; 其中（a）所述金属层包括第一和第二金属的合金，和（b）当所述顶部电极被正偏置时，来自所述第一金属的金属离子在所述SE层中形成导电路径，并且当所述顶部电极是负面的偏见。这里描述了其他实施例。

52. 发明申请

WO2017111930A1 HIGH PERFORMANCE RRAM 审中-公开
标题翻译：高性能RRAM
公开(公告)号：WO2017111930A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067241
申请日：2015-12-22
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , HAMZAOGLU, Fatih , MUKHERJEE, Niloy , MAJHI, Prashant , KARPOV, Elijah V. , SHAH, Uday
IPC分类号： G11C13/00 , G11C11/00
CPC分类号： G11C13/0097 , G11C13/0007 , G11C13/0038 , G11C13/0069 , G11C2013/0083 , G11C2213/15 , H01L28/00
摘要： Embodiments are directed to a resistive random access memory (RRAM) element that includes a top electrode; a bottom electrode; a dielectric material disposed between the top electrode and the bottom electrode; and a conductive filament in the dielectric material electrically connected to the top electrode, the conductive filament including a first width proximate the top electrode larger than a second width proximate the bottom electrode. In some embodiments, the first width includes a larger number of conductive elements than the second width. A wide filament can be formed for a sleep mode that can maintain a threshold conductance (LRS) under no or low power conditions by having a larger number of conductance elements in the no or low power mode than when in a normal operational mode.
摘要翻译：实施例针对包括顶部电极的电阻式随机存取存储器（RRAM）元件; 底部电极; 设置在顶部电极和底部电极之间的介电材料; 以及电介质材料中的导电丝，所述导电丝电连接到所述顶部电极，所述导电丝包括靠近所述顶部电极的第一宽度大于靠近所述底部电极的第二宽度。在一些实施例中，第一宽度包括比第二宽度更大数量的导电元件。对于睡眠模式可以形成宽灯丝，通过在无功率模式或低功率模式下具有比在正常操作模式下更多数量的电导元件，可以在无功率或低功率条件下维持阈值电导（LRS） p>

53. 发明申请

WO2017086921A1 HETEROJUNCTION TFETs EMPLOYING AN OXIDE SEMICONDUCTOR 审中-公开
标题翻译：采用氧化物半导体的杂多功能场效应晶体管
公开(公告)号：WO2017086921A1
公开(公告)日：2017-05-26
申请号：PCT/US2015/060935
申请日：2015-11-16
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , KAVALIEROS, Jack T. , KARPOV, Elijah V. , SHAH, Uday , PILLARISETTY, Ravi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/267 , H01L29/66356 , H01L29/66969 , H01L29/7391
摘要： Heterojunction tunnel field effect transistors (hTFETs) incorporating one or more oxide semiconductor and a band offset between at least one of a channel material, a source material of a first conductivity type, and drain of a second conductivity type, complementary to the first. In some embodiments, at least one of p-type material, channel material and n-type material comprises an oxide semiconductor. In some embodiments, two or more of p-type material, channel material, and n-type material comprises an oxide semiconductor. In some n-type hTFET embodiments, all of p-type, channel, and n-type materials are oxide semiconductors with a type-II or type-III band offset between the p-type and channel material.
摘要翻译：包含一个或多个氧化物半导体的异质结隧道场效应晶体管（hTFET）以及沟道材料，第一导电类型的源材料和第二导电类型的漏极中的至少一个之间的带偏移类型，与第一个互补。在一些实施例中，p型材料，沟道材料和n型材料中的至少一种包括氧化物半导体。在一些实施例中，两种或更多种p型材料，沟道材料和n型材料包括氧化物半导体。在一些n型hTFET实施例中，所有p型，沟道和n型材料都是在p型和沟道材料之间具有偏移类型II或类型III的氧化物半导体。

54. 发明申请

WO2018063320A1 CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY (CBRAM) DEVICES WITH LOW THERMAL CONDUCTIVITY ELECTROLYTE SUBLAYER 审中-公开
标题翻译：具有低导热率的导电桥随机存取存储器（CBRAM）器件电解质流化床
公开(公告)号：WO2018063320A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054748
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , KOTLYAR, Roza , MAJHI, Prashant , BIELEFELD, Jeffery D.
IPC分类号： H01L45/00
CPC分类号： H01L45/08 , G11C13/0011 , G11C2013/0073 , G11C2213/33 , G11C2213/34 , G11C2213/35 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625
摘要： Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.
摘要翻译：描述了具有低导热率电解质子层的导电桥随机存取存储器（CBRAM）器件。在一个示例中，导电桥随机存取存储器（CBRAM）器件包括设置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 CBRAM器件还包括布置在导电互连上的CBRAM元件。 CBRAM元件包括设置在导电互连上的有源电极层和设置在有源电极层上的电阻切换层。电阻切换层包括设置在第二电解质材料层上的第一电解质材料层，第二电解质材料层设置在有源电极层上并且具有比第一电解质材料层的导热率低的导热率。无源电极层设置在电阻切换层的第一电解质材料上。

55. 发明申请

WO2018056963A1 CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY (CBRAM) DEVICES WITH GRADED CONDUCTIVITY ELECTROLYTE LAYER 审中-公开
标题翻译：具有分级导电性电解质层的导电桥随机存取存储器（CBRAM）器件
公开(公告)号：WO2018056963A1
公开(公告)日：2018-03-29
申请号：PCT/US2016/052790
申请日：2016-09-21
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , MUKHERJEE, Niloy , PILLARISETTY, Ravi , MAJHI, Prashant
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , G11C13/0011 , G11C2213/15 , G11C2213/52 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/1625 , H01L45/1641
摘要： Conductive bridge random access memory (CBRAM) devices with graded conductivity electrolyte layers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. A CBRAM element is disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect. A resistance switching layer is disposed above the active electrode layer. A passive electrode layer is disposed above the resistance switching layer. The resistance switching layer has a region of higher conductivity proximate to the passive electrode, the region of higher conductivity above and materially graded to a region of lower conductivity proximate to the underlying active electrode.
摘要翻译：描述了具有渐变电导率电解质层的导电桥随机存取存储器（CBRAM）器件。在一个示例中，导电桥随机存取存储器（CBRAM）器件包括设置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 CBRAM元件设置在导电互连上。 CBRAM元件包括设置在导电互连上的有源电极层。电阻切换层设置在有源电极层上方。无源电极层设置在电阻切换层上方。电阻切换层具有靠近无源电极的较高电导率的区域，该区域具有较高的导电率，并在材料上渐变为接近下面的有源电极的较低电导率的区域。

56. 发明申请

WO2018044257A1 RESISTIVE RANDOM ACCESS MEMORY DEVICES 审中-公开
公开(公告)号：WO2018044257A1
公开(公告)日：2018-03-08
申请号：PCT/US2016/049197
申请日：2016-08-29
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah V. , MUKHERJEE, Niloy , CLARKE, James S.
IPC分类号： H01L45/00
摘要： Disclosed herein are resistive random access memory (RRAM) devices, and related memory cells and electronic devices. In some embodiments, an RRAM device may include a bottom electrode, an oxygen exchange layer (OEL), and an oxide layer. The bottom electrode may be disposed between the OEL and a substrate, and the OEL may be disposed between the oxide layer and the bottom electrode.

57. 发明申请

WO2018009157A1 RESISTIVE RANDOM ACCESS MEMORY (RRAM) WITH MULTICOMPONENT OXIDES 审中-公开
标题翻译：随机访问存储器（RRAM）与多组分氧化物
公开(公告)号：WO2018009157A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040893
申请日：2016-07-02
申请人： INTEL CORPORATION
发明人： MUKHERJEE, Niloy , KARPOV, Elijah V. , PILLARISETTY, Ravi , CLARKE, James S.
IPC分类号： H01L45/00 , G11C13/00
摘要： A memory including a top electrode and a bottom electrode; and an oxide layer including a plurality of intimately mixed oxides throughout the oxide layer. A memory including a top electrode and a bottom electrode; an oxygen exchange layer; and an oxide layer between the oxygen exchanger layer and the bottom electrode, wherein the oxide layer includes of a plurality of intimately mixed oxides. A method including forming a bottom electrode; forming an oxide layer on the bottom electrode wherein the oxide layer includes a plurality of intimately mixed oxides throughout the oxide layer; forming an oxygen exchange layer (OEL) on the oxide layer; and forming a top electrode on the OEL.
摘要翻译：包括顶部电极和底部电极的存储器; 以及遍及氧化物层包括多个紧密混合的氧化物的氧化物层。存储器，包括顶部电极和底部电极; 氧交换层; 以及在所述氧交换器层和所述底部电极之间的氧化物层，其中所述氧化物层包含多种紧密混合的氧化物。一种方法，包括形成底部电极; 在所述底部电极上形成氧化物层，其中所述氧化物层包括贯穿所述氧化物层的多个紧密混合的氧化物; 在氧化物层上形成氧交换层（OEL）并在OEL上形成顶部电极。

58. 发明申请

WO2018004588A1 APPROACHES FOR FABRICATING BACK END OF LINE (BEOL)-COMPATIBLE RRAM DEVICES AND THE RESULTING STRUCTURES 审中-公开
标题翻译：用于制作线性（栅格）可兼容RRAM器件的后端和导致结构的方法
公开(公告)号：WO2018004588A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040302
申请日：2016-06-30
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , INDUKURI, Tejaswi K. , PILLARISETTY, Ravi , SHAH, Uday , MUKHERJEE, Niloy , KARPOV, Elijah V. , CLARKE, James S.
IPC分类号： H01L45/00
CPC分类号： H01L45/00 , G11C13/0007 , G11C2013/0073 , G11C2213/11 , H01L27/2436 , H01L45/08 , H01L45/145
摘要： Approaches for fabricating back end of line (BEOL)-compatible resistive random access memory (RRAM) elements and devices, and the resulting structures, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The ILD layer has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect. An RRAM element is disposed on the conductive interconnect. The RRAM element includes a first electrode layer disposed on the uppermost surface of the conductive interconnect, a resistance switching layer disposed on the first electrode layer, and a second electrode layer disposed on the resistance switching layer. An insulating metal oxide layer is disposed on the uppermost surface of the ILD layer and laterally adjacent to and in contact with the first electrode layer.
摘要翻译：描述了用于制造线后端（BEOL）兼容电阻随机存取存储器（RRAM）元件和器件以及所得结构的方法。在一个示例中，电阻随机存取存储器（RRAM）器件包括布置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 ILD层具有与导电互连的最上表面基本共面的最上表面。 RRAM元件设置在导电互连上。 RRAM元件包括布置在导电互连的最上表面上的第一电极层，布置在第一电极层上的电阻切换层以及布置在电阻切换层上的第二电极层。绝缘金属氧化物层设置在ILD层的最上表面上并与第一电极层横向相邻并与第一电极层接触。

59. 发明申请

WO2018004574A1 RRAM DEVICES WITH AMORPHOUS BOTTOM BALLAST LAYER 审中-公开
标题翻译： RRAM器件具有无定形底部镇流器层
公开(公告)号：WO2018004574A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040203
申请日：2016-06-29
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , SHAH, Uday , KARPOV, Elijah V. , PILLARISETTY, Ravi , INDUKURI, Tejaswi K. , MUKHERJEE, Niloy , CLARKE, James S.
IPC分类号： G11C13/00 , H01L27/24 , H01L45/00
摘要： Approaches for fabricating RRAM stacks with an amorphous bottom ballast layer, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. An RRAM element is disposed on the conductive interconnect. The RRAM element includes a first electrode layer disposed on the uppermost surface of the conductive interconnect. An amorphous ballast layer is disposed on the first electrode layer. A resistance switching layer is disposed on the amorphous ballast layer. The amorphous ballast layer is separate and distinct from the first electrode layer and from the resistance switching layer. A second electrode layer is disposed above the resistance switching layer.
摘要翻译：描述了制造具有无定形底部压载层的RRAM堆栈的方法以及所得到的结构和器件。在一个示例中，电阻随机存取存储器（RRAM）器件包括布置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 RRAM元件设置在导电互连上。 RRAM元件包括设置在导电互连的最上表面上的第一电极层。非晶态压载层设置在第一电极层上。电阻切换层设置在非晶形压载层上。非晶形压载层与第一电极层和电阻切换层分开并且不同。第二电极层设置在电阻切换层上方。

60. 发明申请

WO2017171819A1 RESISTIVE RANDOM ACCESS MEMORY WITH DEUTERIUM 审中-公开
标题翻译：具有氘的随机访问存储器
公开(公告)号：WO2017171819A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025430
申请日：2016-03-31
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , PILLARISETTY, Ravi , SHAH, Uday , KARPOV, Elijah V. , MUKHERJEE, Niloy , JAIN, Pulkit , KILLAMPALLI, Aravind S. , GUPTA, Jay P. , CLARKE, James S.
IPC分类号： H01L45/00 , H01L45/02
摘要： An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.
摘要翻译：一个实施例包括一种存储器，该存储器包括：顶部电极和底部电极; 顶部电极和底部电极之间的氧气交换层（OEL）以及OEL和底部电极之间的氧化物层; 其中氧化物层包括氘和氧空位。这里描述了其他实施例。

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