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51. 发明申请

WO2019125352A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT MEMORY CELL HAVING A FERROELECTRIC FIELD EFFECT TRANSISTOR WITH A FLOATING GATE 审中-公开
公开(公告)号：WO2019125352A1
公开(公告)日：2019-06-27
申请号：PCT/US2017/066932
申请日：2017-12-18
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah , DOYLE, Brian , SHARMA, Abhishek , MAJHI, Prashant , PILLARISETTY, Ravi
IPC分类号： H01L27/11585 , H01L27/11502 , H01L21/28 , H01L21/768
摘要： A three-dimensional integrated circuit memory device may be fabricated to have memory cells comprising a layered stack structure formed from a plurality of dielectric layers and at least one conductive layer positioned between adjacent dielectric layers of the plurality of dielectric layers. A via may be defined by a sidewall extending through the layered stack structure and a gate dielectric layer may be formed within the via. A channel material layer may be formed within the via contacting the gate dielectric layer. A floating gate material layer may be formed between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer. A ferroelectric material layer may be formed between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.

52. 发明申请

WO2019066854A1 DYNAMIC RANDOM ACCESS MEMORY INCLUDING THRESHOLD SWITCH 审中-公开
公开(公告)号：WO2019066854A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054016
申请日：2017-09-28
申请人： INTEL CORPORATION
发明人： SHARMA, Abhishek A. , PILLARISETTY, Ravi , DOYLE, Brian S. , MAJHI, Prashant
IPC分类号： H01L27/108
摘要： Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.

53. 发明申请

WO2018063320A1 CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY (CBRAM) DEVICES WITH LOW THERMAL CONDUCTIVITY ELECTROLYTE SUBLAYER 审中-公开
标题翻译：具有低导热率的导电桥随机存取存储器（CBRAM）器件电解质流化床
公开(公告)号：WO2018063320A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054748
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , KOTLYAR, Roza , MAJHI, Prashant , BIELEFELD, Jeffery D.
IPC分类号： H01L45/00
CPC分类号： H01L45/08 , G11C13/0011 , G11C2013/0073 , G11C2213/33 , G11C2213/34 , G11C2213/35 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625
摘要： Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.
摘要翻译：描述了具有低导热率电解质子层的导电桥随机存取存储器（CBRAM）器件。在一个示例中，导电桥随机存取存储器（CBRAM）器件包括设置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 CBRAM器件还包括布置在导电互连上的CBRAM元件。 CBRAM元件包括设置在导电互连上的有源电极层和设置在有源电极层上的电阻切换层。电阻切换层包括设置在第二电解质材料层上的第一电解质材料层，第二电解质材料层设置在有源电极层上并且具有比第一电解质材料层的导热率低的导热率。无源电极层设置在电阻切换层的第一电解质材料上。

54. 发明申请

WO2018056963A1 CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY (CBRAM) DEVICES WITH GRADED CONDUCTIVITY ELECTROLYTE LAYER 审中-公开
标题翻译：具有分级导电性电解质层的导电桥随机存取存储器（CBRAM）器件
公开(公告)号：WO2018056963A1
公开(公告)日：2018-03-29
申请号：PCT/US2016/052790
申请日：2016-09-21
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , MUKHERJEE, Niloy , PILLARISETTY, Ravi , MAJHI, Prashant
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , G11C13/0011 , G11C2213/15 , G11C2213/52 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/1625 , H01L45/1641
摘要： Conductive bridge random access memory (CBRAM) devices with graded conductivity electrolyte layers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. A CBRAM element is disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect. A resistance switching layer is disposed above the active electrode layer. A passive electrode layer is disposed above the resistance switching layer. The resistance switching layer has a region of higher conductivity proximate to the passive electrode, the region of higher conductivity above and materially graded to a region of lower conductivity proximate to the underlying active electrode.
摘要翻译：描述了具有渐变电导率电解质层的导电桥随机存取存储器（CBRAM）器件。在一个示例中，导电桥随机存取存储器（CBRAM）器件包括设置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 CBRAM元件设置在导电互连上。 CBRAM元件包括设置在导电互连上的有源电极层。电阻切换层设置在有源电极层上方。无源电极层设置在电阻切换层上方。电阻切换层具有靠近无源电极的较高电导率的区域，该区域具有较高的导电率，并在材料上渐变为接近下面的有源电极的较低电导率的区域。

55. 发明申请

WO2018044257A1 RESISTIVE RANDOM ACCESS MEMORY DEVICES 审中-公开
公开(公告)号：WO2018044257A1
公开(公告)日：2018-03-08
申请号：PCT/US2016/049197
申请日：2016-08-29
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah V. , MUKHERJEE, Niloy , CLARKE, James S.
IPC分类号： H01L45/00
摘要： Disclosed herein are resistive random access memory (RRAM) devices, and related memory cells and electronic devices. In some embodiments, an RRAM device may include a bottom electrode, an oxygen exchange layer (OEL), and an oxide layer. The bottom electrode may be disposed between the OEL and a substrate, and the OEL may be disposed between the oxide layer and the bottom electrode.

56. 发明申请

WO2018004588A1 APPROACHES FOR FABRICATING BACK END OF LINE (BEOL)-COMPATIBLE RRAM DEVICES AND THE RESULTING STRUCTURES 审中-公开
标题翻译：用于制作线性（栅格）可兼容RRAM器件的后端和导致结构的方法
公开(公告)号：WO2018004588A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040302
申请日：2016-06-30
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , INDUKURI, Tejaswi K. , PILLARISETTY, Ravi , SHAH, Uday , MUKHERJEE, Niloy , KARPOV, Elijah V. , CLARKE, James S.
IPC分类号： H01L45/00
CPC分类号： H01L45/00 , G11C13/0007 , G11C2013/0073 , G11C2213/11 , H01L27/2436 , H01L45/08 , H01L45/145
摘要： Approaches for fabricating back end of line (BEOL)-compatible resistive random access memory (RRAM) elements and devices, and the resulting structures, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The ILD layer has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect. An RRAM element is disposed on the conductive interconnect. The RRAM element includes a first electrode layer disposed on the uppermost surface of the conductive interconnect, a resistance switching layer disposed on the first electrode layer, and a second electrode layer disposed on the resistance switching layer. An insulating metal oxide layer is disposed on the uppermost surface of the ILD layer and laterally adjacent to and in contact with the first electrode layer.
摘要翻译：描述了用于制造线后端（BEOL）兼容电阻随机存取存储器（RRAM）元件和器件以及所得结构的方法。在一个示例中，电阻随机存取存储器（RRAM）器件包括布置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 ILD层具有与导电互连的最上表面基本共面的最上表面。 RRAM元件设置在导电互连上。 RRAM元件包括布置在导电互连的最上表面上的第一电极层，布置在第一电极层上的电阻切换层以及布置在电阻切换层上的第二电极层。绝缘金属氧化物层设置在ILD层的最上表面上并与第一电极层横向相邻并与第一电极层接触。

57. 发明申请

WO2018004574A1 RRAM DEVICES WITH AMORPHOUS BOTTOM BALLAST LAYER 审中-公开
标题翻译： RRAM器件具有无定形底部镇流器层
公开(公告)号：WO2018004574A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040203
申请日：2016-06-29
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , SHAH, Uday , KARPOV, Elijah V. , PILLARISETTY, Ravi , INDUKURI, Tejaswi K. , MUKHERJEE, Niloy , CLARKE, James S.
IPC分类号： G11C13/00 , H01L27/24 , H01L45/00
摘要： Approaches for fabricating RRAM stacks with an amorphous bottom ballast layer, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. An RRAM element is disposed on the conductive interconnect. The RRAM element includes a first electrode layer disposed on the uppermost surface of the conductive interconnect. An amorphous ballast layer is disposed on the first electrode layer. A resistance switching layer is disposed on the amorphous ballast layer. The amorphous ballast layer is separate and distinct from the first electrode layer and from the resistance switching layer. A second electrode layer is disposed above the resistance switching layer.
摘要翻译：描述了制造具有无定形底部压载层的RRAM堆栈的方法以及所得到的结构和器件。在一个示例中，电阻随机存取存储器（RRAM）器件包括布置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 RRAM元件设置在导电互连上。 RRAM元件包括设置在导电互连的最上表面上的第一电极层。非晶态压载层设置在第一电极层上。电阻切换层设置在非晶形压载层上。非晶形压载层与第一电极层和电阻切换层分开并且不同。第二电极层设置在电阻切换层上方。

58. 发明申请

WO2017171819A1 RESISTIVE RANDOM ACCESS MEMORY WITH DEUTERIUM 审中-公开
标题翻译：具有氘的随机访问存储器
公开(公告)号：WO2017171819A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025430
申请日：2016-03-31
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , PILLARISETTY, Ravi , SHAH, Uday , KARPOV, Elijah V. , MUKHERJEE, Niloy , JAIN, Pulkit , KILLAMPALLI, Aravind S. , GUPTA, Jay P. , CLARKE, James S.
IPC分类号： H01L45/00 , H01L45/02
摘要： An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.
摘要翻译：一个实施例包括一种存储器，该存储器包括：顶部电极和底部电极; 顶部电极和底部电极之间的氧气交换层（OEL）以及OEL和底部电极之间的氧化物层; 其中氧化物层包括氘和氧空位。这里描述了其他实施例。

59. 发明申请

WO2017171780A1 1T1R RRAM ARCHITECTURE 审中-公开
标题翻译： 1T1R RRAM架构
公开(公告)号：WO2017171780A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025179
申请日：2016-03-31
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , KARPOV, Elijah V. , PILLARISETTY, Ravi , SHAH, Uday , MUKHERJEE, Niloy , CLARKE, James S.
IPC分类号： H01L45/00 , H01L45/02
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： One embodiment provides an apparatus. The apparatus includes a first memory cell and a second memory cell. The first memory cell includes a first resistive element. The first resistive element includes a first top electrode, a common bottom electrode, and a first oxide layer sandwiched between the first top electrode and at least a first portion of the common bottom electrode. The second memory cell includes a second resistive element adjacent the first resistive element. The second resistive element includes a second top electrode, the common bottom electrode, and a second oxide layer sandwiched between the second top electrode and at least a second portion of the common bottom electrode.
摘要翻译：一个实施例提供了一种装置。该装置包括第一存储单元和第二存储单元。第一存储器单元包括第一电阻元件。第一电阻元件包括第一顶部电极，公共底部电极和夹在第一顶部电极和公共底部电极的至少第一部分之间的第一氧化物层。第二存储器单元包括与第一电阻元件相邻的第二电阻元件。第二电阻元件包括第二顶部电极，公共底部电极和夹在第二顶部电极和公共底部电极的至少第二部分之间的第二氧化物层。

60. 发明申请

WO2017112057A1 METHOD AND APPARATUS FOR MAKING P-CHANNEL THIN FILM TRANSISTORS FOR OLED AND LED ACTIVE MATRIX FLAT PANEL DISPLAYS 审中-公开
标题翻译：制造用于OLED和LED有源矩阵平板显示器的P通道薄膜晶体管的方法和设备
公开(公告)号：WO2017112057A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/057542
申请日：2016-10-18
申请人： INTEL CORPORATION
发明人： AHMED, Khaled , MAJHI, Prashant
IPC分类号： H01L27/12 , H01L27/32 , H01L29/786 , H01L21/02
CPC分类号： H01L29/78696 , H01L21/02565 , H01L21/02584 , H01L21/02631 , H01L21/385 , H01L21/425 , H01L21/477 , H01L27/1225 , H01L27/127 , H01L29/247 , H01L29/66969 , H01L29/7869 , H01L29/78693
摘要： Embodiments of the invention include sulfur alloyed InGaZnO (IGZOS) thin film transistors (TFTs) and methods of making such devices. In one embodiment, the IGZOS TFT may include a substrate and a gate electrode formed over the substrate. A gate dielectric layer may be formed over the gate electrode. An IGZOS film may be formed over a surface of the gate dielectric. Additionally, embodiments of the invention include a source region and a drain region formed in contact with the IGZOS film. An opening between the source region and the drain region may define a channel region in the IGZOS film. Embodiments of the invention are able to form a p-type IGZO TFT by increasing the valence band of the IGZO material in order to eliminate the presence of trap states in the band gap. The valance band may be raised by doping the IGZO material with sulfur.
摘要翻译：本发明的实施例包括硫合金化的InGaZnO（IGZOS）薄膜晶体管（TFT）以及制造这种器件的方法。在一个实施例中，IGZOS TFT可以包括衬底和在衬底上形成的栅电极。栅电介质层可以形成在栅电极上。 IGZOS膜可以形成在栅极电介质的表面上。另外，本发明的实施例包括形成为与IGZOS膜接触的源极区和漏极区。源极区和漏极区之间的开口可以限定IGZOS膜中的沟道区。本发明的实施例能够通过增加IGZO材料的价带来形成p型IGZO TFT，以消除带隙中陷阱状态的存在。通过用硫掺杂IGZO材料可以提高价带。

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