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41. 发明申请

WO2016160165A1 COST OPTIMIZED SINGLE LEVEL CELL MODE NON-VOLATILE MEMORY FOR MULTIPLE LEVEL CELL MODE NON-VOLATILE MEMORY 审中-公开
标题翻译：成本优化的单级单元模式非易失性存储器，用于多级单元模式非易失性存储器
公开(公告)号：WO2016160165A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/018518
申请日：2016-02-18
申请人： INTEL CORPORATION
发明人： RAMALINGAM, Anand S.
IPC分类号： G11C11/56 , G11C16/10 , G06F12/02
CPC分类号： G11C11/1675 , G06F12/0238 , G06F2212/7205 , G06F2212/7208 , G11C11/5628 , G11C13/0004 , G11C13/0035 , G11C13/0069 , G11C16/0483 , G11C16/3495 , G11C2211/5641 , G11C2213/71
摘要： Methods and apparatus related to cost optimized Single Level Cell (SLC) write buffering for Three Level Cell (TLC) Solid State Drives (SSDs) are described. In one embodiment, non-volatile memory includes a first region in a Single Level Cell (SLC) mode and a second region in a multiple level cell mode. A portion of the second region is moved from the multiple level cell mode to the SLC mode, without adding any new capacity to the non-volatile memory and without reducing any existing capacity from the non-volatile memory. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与三电平（TLC）固态硬盘（SSD）的成本优化单电平（SLC）写缓冲相关的方法和设备。在一个实施例中，非易失性存储器包括单级单元（SLC）模式中的第一区域和多级单元模式中的第二区域。第二区域的一部分从多级单元模式移动到SLC模式，而不向非易失性存储器增加任何新的容量，并且不减少来自非易失性存储器的任何现有容量。还公开并要求保护其他实施例。

42. 发明申请

WO2016137545A1 PROGRAM VERIFY FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：程序验证非易失性存储
公开(公告)号：WO2016137545A1
公开(公告)日：2016-09-01
申请号：PCT/US2015/061666
申请日：2015-11-19
申请人： SanDisk Technologies LLC
发明人： SUN, Yongke , YUAN, Jiahui , DONG, Yingda
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C11/5642 , G11C11/5628 , G11C11/5671 , G11C16/0458 , G11C16/32 , G11C16/34 , G11C16/3436 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A non-volatile storage system includes a plurality of non-volatile storage elements arranged in two dimensional or three dimensional structures. The system applies programming to the non-volatile storage elements and performs verification of the programming. The verification includes performing a multi-strobe sensing operation to test for multiple data states while applying a common word line voltage.
摘要翻译：非易失性存储系统包括以二维或三维结构排列的多个非易失性存储元件。系统将编程应用于非易失性存储元件，并执行编程的验证。验证包括执行多次选通感测操作以在施加公共字线电压的同时测试多个数据状态。

43. 发明申请

WO2016118234A1 PARTIAL BLOCK ERASE FOR BLOCK PROGRAMMING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器中的块编程的部分块擦除
公开(公告)号：WO2016118234A1
公开(公告)日：2016-07-28
申请号：PCT/US2015/062781
申请日：2015-11-25
申请人： SanDisk Technologies LLC
发明人： LAI, Chun-Hung , YIN, Cheng-Kuan , LEE, Shih-Chung , DUTTA, Deepanshu , OOWADA, Ken
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3431 , G11C16/349 , G11C2211/5648 , G11C2216/24
摘要： A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.
摘要翻译：非易失性存储器系统在编程操作期间利用部分块擦除来减轻编程通过电压干扰的影响。接收与来自块的一组字线相关联的编程请求，例如字线的全部或一部分。在开始编程之前，系统擦除并软编程块。系统编程用于编程请求的块的字线的子集。在对字线子集编程之后，系统暂停编程操作，并对块的未编程字线执行擦除操作。可以在擦除操作期间禁止已经编程的字线和一个或多个可选的缓冲字线擦除。在擦除未编程的字线之后，系统通过对块的未编程区域中剩余的用户数据进行编程来完成编程请求。

44. 发明申请

WO2016118225A1 METHOD AND APPARATUS FOR REFRESH PROGRAMMING OF MEMORY CELLS BASED ON AMOUNT OF THRESHOLD VOLTAGE DOWNSHIFT 审中-公开
标题翻译：基于阈值电压梯度的存储器细胞刷新编程的方法和装置
公开(公告)号：WO2016118225A1
公开(公告)日：2016-07-28
申请号：PCT/US2015/061441
申请日：2015-11-18
申请人： SanDisk Technologies LLC
发明人： PANG, Liang , DONG, Yingda , CHEN, Jian
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3431 , G11C11/5621 , G11C11/5671 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3459
摘要： Techniques are provided for periodically monitoring and adjusting the threshold voltage levels of memory cells in a charge-trapping memory device. When a criterion is met, such as based on the passage of a specified time period, the memory cells are read to classify them into different subsets according to an amount of downshift in threshold voltage (Vth). Two or more subsets can be used per data state. A subset can also comprise cells which are corrected using Error Correction Code (ECC) decoding. The subsets of memory cells are refresh programmed, without being erased, in which a Vth upshift is provided in proportion to the Vth downshift. The refresh programming can use a fixed or adaptive number of program pulses per subset. Some cells will have no detectable Vth downshift or a minor amount of Vth downshift which can be ignored. These cells need not be refresh programmed.
摘要翻译：提供了用于周期性地监视和调整电荷俘获存储器件中的存储器单元的阈值电压电平的技术。当满足标准时，例如基于指定时间段的过去，存储器单元被读取以根据阈值电压（Vth）的降档量将其分类成不同的子集。每个数据状态可以使用两个或多个子集。子集还可以包括使用纠错码（ECC）解码来校正的单元。存储器单元的子集被刷新编程，而不被擦除，其中与Vth降档成比例地提供Vth升档。刷新编程可以使用每个子集的固定或自适应编程脉冲数。一些电池将没有可检测的Vth降档或少量的Vth降档，这可以被忽略。这些单元不需要刷新编程。

45. 发明申请

WO2016081061A1 PARTIAL ERASE OF NONVOLATILE MEMORY BLOCKS 审中-公开
标题翻译：部分擦除非易失性存储块
公开(公告)号：WO2016081061A1
公开(公告)日：2016-05-26
申请号：PCT/US2015/051248
申请日：2015-09-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： YANG, Nian Niles , HUANG, Jianmin
IPC分类号： G11C11/56 , G11C16/16
CPC分类号： G11C16/16 , G06F12/0246 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/3445
摘要： Erasing blocks of a nonvolatile memory may include two erase steps. A first erase step brings the memory cells of a block to an intermediate state between their programmed states and an erased state. The block is then maintained with the memory cells in the intermediate state for a period of time. Subsequently, a second erase step on the block brings the memory cells from the intermediate state to the erased state.
摘要翻译：非易失性存储器的擦除块可以包括两个擦除步骤。第一擦除步骤使块的存储单元在其编程状态和擦除状态之间达到中间状态。然后将该块与处于中间状态的存储单元保持一段时间。随后，块上的第二擦除步骤使存储器单元从中间状态到擦除状态。

46. 发明申请

WO2016069147A1 WORD LINE DEPENDENT TWO STROBE SENSING MODE FOR NONVOLATILE STORAGE ELEMENTS 审中-公开
标题翻译：非线性存储元件的字线相关的两个结构感测模式
公开(公告)号：WO2016069147A1
公开(公告)日：2016-05-06
申请号：PCT/US2015/052076
申请日：2015-09-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： DUTTA, Deepanshu , MIAO, Xiaochang , HEMINK, Gerrit Jan
IPC分类号： G11C11/56 , G11C16/26 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/3427
摘要： A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the nonvolatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the nonvolatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a one strobe sensing process or a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements, depending on whether the selected word line is within a threshold distance of a charging source for the selected bit lines.
摘要翻译：非易失性存储系统包括多个非易失性存储元件，连接到非易失性存储元件的多个位线，连接到非易失性存储元件的多个字线以及连接到非易失性存储元件的一个或多个控制电路位线和字线。一个或多个控制电路对非易失性存储元件执行编程，验证，读取和擦除。当验证时，连接到非易失性存储元件的位线的第一子集被充电以允许感测，而位线的第二子集不被充电。当读取时，根据所选择的字线是否在所选择的位的充电源的阈值距离内，选择性地使用一个选通感测处理或两个选通感测处理以更准确地从非易失性存储元件读取数据线。

47. 发明申请

WO2016049474A1 LOGIC HIGH-DIELECTRIC-CONSTANT (HK) METAL-GATE (MG) ONE-TIME-PROGRAMMING (OTP) MEMORY DEVICE SENSING METHOD 审中-公开
标题翻译：逻辑高介电常数（HK）金属门（MG）一次编程（OTP）存储器件感应方法
公开(公告)号：WO2016049474A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052252
申请日：2015-09-25
申请人： QUALCOMM INCORPORATED
发明人： LI, Xia , CHEN, Xiaonan , LU, Xiao
IPC分类号： G11C17/16 , G11C17/18 , G11C13/00 , G11C11/56
CPC分类号： G11C17/18 , G11C11/5692 , G11C17/16
摘要： In a one-time-programming (OTP) memory cell, dual-voltage sensing is utilized to determine whether the memory cell has experienced a non/soft breakdown or a hard breakdown. The drain current of the memory cell is read when the gate voltage is at a first predetermined voltage, and if the read drain current is greater than a predetermined current level, then a hard breakdown is detected. One or more additional readings of the current may be obtained to determine that a hard breakdown has occurred. If the read drain current is less than the predetermined current level, then a non/soft breakdown is detected. The threshold voltage of the memory cell may be shifted, and a second reading of the drain current may be obtained when the gate voltage is at a second predetermined voltage in case the memory cell experiences a non/soft breakdown.
摘要翻译：在一次编程（OTP）存储器单元中，利用双电压感测来确定存储器单元是否经历了非/软故障或硬故障。当栅极电压处于第一预定电压时，读取存储单元的漏极电流，并且如果读取的漏极电流大于预定电流电平，则检测到硬故障。可以获得电流的一个或多个附加读数以确定发生了硬故障。如果读漏极电流小于预定电流电平，则检测到非/软击穿。当存储器单元经历非/软击穿时，当栅极电压处于第二预定电压时，可以移位存储单元的阈值电压，并且可以获得漏极电流的第二读数。

48. 发明申请

WO2016032706A1 PROGRAMMING MEMORY WITH REDUCED SHORT-TERM CHARGE LOSS 审中-公开
标题翻译：具有减少短期充电损失的编程存储器
公开(公告)号：WO2016032706A1
公开(公告)日：2016-03-03
申请号：PCT/US2015/043728
申请日：2015-08-05
申请人： SANDISK TECHNOLOGIES INC.
发明人： LU, Ching-Huang , DONG, Yingda , PANG, Liang , KUO, Tien-Chien
IPC分类号： G11C16/34 , G11C16/10 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0466 , G11C16/3404 , G11C16/3459
摘要： Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programing pass (801) in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied (807) to control gates of the memory cells. Subsequently, a final programming pass is performed (808) in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programing pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.
摘要翻译：提供了在编程电荷俘获存储器单元时减少短期电荷损失的影响的技术。短时间的电荷损失可导致降档和阈值电压分布的扩大。编程操作包括对于每个目标数据状态，将存储器单元编程为接近最终阈值电压分布的粗略编程遍（801）。随后，施加负电压（807）以控制存储器单元的栅极。随后，执行最终编程遍（808），其中将存储器单元编程为最终阈值电压分布。由于负电压加速电荷损失，因此在最终编程通过后电荷损失减小。粗略编程通过可以使用增量步进脉冲编程来获得最低目标数据状态，以获得关于编程速度的信息。可以根据编程速度设置最终编程遍历中的初始编程电压。

49. 发明申请

WO2016020760A2 ADAPTIVE FLASH TUNING 审中-公开
标题翻译：自适应FLASH调节
公开(公告)号：WO2016020760A2
公开(公告)日：2016-02-11
申请号：PCT/IB2015001849
申请日：2015-08-04
申请人： RYAN CONOR MAURICE , SULLIVAN JOSEPH
发明人： RYAN CONOR MAURICE , SULLIVAN JOSEPH
IPC分类号： G06F3/06 , G11C11/56 , G11C16/20 , G11C16/34
CPC分类号： G11C29/52 , G06F3/0605 , G06F3/061 , G06F3/0616 , G06F3/0634 , G06F3/064 , G06F3/0649 , G06F3/0653 , G06F3/0655 , G06F3/0659 , G06F3/0664 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1009 , G06F13/24 , G06F2212/1036 , G06F2212/2022 , G06F2212/7201 , G06F2212/7211 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/349 , G11C29/36 , G11C29/38 , G11C29/44 , G11C29/50012
摘要： The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, "test chips" from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods).
摘要翻译：本发明包括用于通过监视设备及其设备的健康状况来提高操作效率并延长闪存存储设备（及其组件快闪存储器芯片，LUN和闪存存储器块）的估计操作寿命的系统和方法的实施例并且作为响应，在其操作寿命期间自适应地调整闪存芯片的操作参数，以及在此期间采用其他较不重要的预防措施，通过接口避免需要直接访问闪存的测试模式内存芯片。在离线特征化阶段，使用来自一批最近制造的闪存芯片的“测试芯片”来模拟各种使用场景并测量写入的性能影响并尝试恢复（读取）以不同的操作参数组写入的测试模式时间（模拟所需的保留时间）。

50. 发明申请

WO2016011638A1 相变存储器的数据存储方法及控制装置审中-公开
公开(公告)号：WO2016011638A1
公开(公告)日：2016-01-28
申请号：PCT/CN2014/082918
申请日：2014-07-24
申请人：华为技术有限公司
发明人：李震 , 何强 , 缪向水 , 徐荣刚 , 赵俊峰 , 韦竹林
IPC分类号： G11C16/02 , G11C11/56
CPC分类号： G11C13/0069 , G11C7/02 , G11C11/5678 , G11C13/0033 , G11C13/0097 , G11C2013/0092
摘要：一种相变存储器的数据存储方法及控制装置。该方法包括：获取待存储数据，该待存储数据为多位数据（S101）；根据该待存储数据，产生擦脉冲信号和写脉冲信号，该写脉冲信号为包括至少两个连续脉冲的信号，该至少两个连续脉冲的间隔相同，且该至少两个连续脉冲的间隔为根据该待存储数据而确定的值（S102）；将该擦脉冲信号施加至该相变存储器的存储单元使该存储单元变为晶态（S103）；将该写脉冲信号施加至该存储单元使该存储单元变为第一电阻值的非晶态，以通过该存储单元的第一电阻值的非晶态表征所述待存储数据（S104）。可解决多值存储时的热串扰问题。

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