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41. 发明申请

WO2014198734A1 SEMICONDUCTOR SWITCHING STRING 审中-公开
标题翻译：半导体开关STRING
公开(公告)号：WO2014198734A1
公开(公告)日：2014-12-18
申请号：PCT/EP2014/062049
申请日：2014-06-10
申请人： ALSTOM TECHNOLOGY LTD
发明人： DAVIDSON, Colin Charnock
IPC分类号： H03K17/0814 , H02M1/06 , H02M3/18
CPC分类号： H03K17/161 , H02M5/45 , H02M5/458 , H02M7/68 , H03K17/08144 , H03K17/105 , H03K17/16 , H03K17/66 , H03K17/687
摘要： In the field of HVDC power converters there is a need for an improved semiconductor switching string which obviates the difficulties associated with respective semiconductor switching elements exhibiting different performance characteristics and having inherent limitations in their performance. A semiconductor switching string (100), for use in a HVDC power converter, comprises a plurality of series-connected semiconductor switching assemblies (10; 70; 110). Each semiconductor switching assembly (10; 70; 110) has a main semiconductor switching element (12) that includes first and second connection terminals (14, 16) between which current flows from the first terminal (14) to the second terminal (16) when the main semiconductor switching element (12) is switched on. The main semiconductor switching element (12) also has an auxiliary semiconductor switching element (28; 72; 1 12) electrically connected between the first and second connection terminals (14, 16) thereof. Each semiconductor switching assembly (10; 70; 110) also includes a control unit (30) which is operatively connected with each auxiliary semiconductor switching element (28; 72; 112). The or each control unit (30) is configured to switch on a respective auxiliary semiconductor switching element (28; 72; 112) to selectively create an alternative current path (32; 114, 116) between the first and second connection terminals (14, 16) associated therewith whereby current is diverted to flow through the alternative current path (32; 114, 116) to reduce the voltage across the corresponding main semiconductor switching element (12). The or each control unit (30) is further configured to switch on the said respective auxiliary semiconductor switching element (28; 72; 112) when the voltage across the corresponding main semiconductor switching element (12) differs from a voltage reference derived from the voltage across all of the main semiconductor switching elements (12) in the semiconductor switching string (100).
摘要翻译：在HVDC功率转换器的领域中，需要一种改进的半导体开关串，其消除了与表现出不同性能特征的各个半导体开关元件相关联的困难并且其性能具有固有的局限性。一种用于HVDC功率转换器的半导体开关串（100）包括多个串联连接的半导体开关组件（10; 70; 110）。每个半导体开关组件（10; 70; 110）具有主半导体开关元件（12），其包括第一和第二连接端子（14,16），电流从第一端子（14）流到第二端子（16）当主半导体开关元件（12）接通时。主半导体开关元件（12）还具有电连接在其第一和第二连接端子（14,16）之间的辅助半导体开关元件（28; 72; 112）。每个半导体开关组件（10; 70; 110）还包括与每个辅助半导体开关元件（28; 72; 112）可操作地连接的控制单元（30）。所述或每个控制单元（30）被配置为接通相应的辅助半导体开关元件（28; 72; 112），以选择性地在第一和第二连接端子（14， 16），由此电流被转向流过替代电流路径（32; 114,116）以减小相应主半导体开关元件（12）两端的电压。或者每个控制单元（30）还被配置为当相应的主半导体开关元件（12）两端的电压与源自电压的电压基准不同时，接通所述相应的辅助半导体开关元件（28; 72; 112）跨越半导体开关串（100）中的所有主要半导体开关元件（12）。

42. 发明申请

WO2014198730A1 SEMICONDUCTOR SWITCHING CIRCUIT 审中-公开
标题翻译：半导体开关电路
公开(公告)号：WO2014198730A1
公开(公告)日：2014-12-18
申请号：PCT/EP2014/062043
申请日：2014-06-10
申请人： ALSTOM TECHNOLOGY LTD
发明人： DAVIDSON, Colin Charnock
IPC分类号： H03K17/0814 , H02M1/06 , H02M3/18
CPC分类号： H03K17/161 , H02M5/45 , H02M5/458 , H02M7/68 , H03K17/08144 , H03K17/105 , H03K17/16 , H03K17/66 , H03K17/687
摘要： In the field of HVDC power converters there is a need for an improved semiconductor switching circuit which obviates the difficulties associated with respective semiconductor switching elements exhibiting different performance characteristics and having inherent limitations in their performance. A semiconductor switching circuit (70; 80; 90) comprises a main current branch (74; 92) which includes at least one main semiconductor switching element (12) and through which current flows in a first direction (D 1 ) when the or each main semiconductor switching element (12) is switched on. The semiconductor switching circuit (70; 80; 90) also includes an auxiliary current branch (76; 104) that is connected in parallel with the main current branch (74; 92). The auxiliary current branch (76; 104) includes at least one auxiliary semiconductor switching element (72) and the or each auxiliary semiconductor switching element (72) has a control unit (30) operatively connected therewith. The or each control unit (30) is configured to switch on the or each auxiliary semiconductor switching element (72) in the auxiliary current branch (76; 104) as the or each main semiconductor switching element (12) is switched on to selectively create an alternative current path (32; 108) via the auxiliary current branch (76; 104) whereby current flowing in the first direction (D 1 ) through the main current branch (74; 92) is diverted instead to flow through the alternative current path (32; 108) to reduce the rate of change of current flowing through the or each main semiconductor switching element (12) immediately after the or each said main semiconductor switching element (12) is switched on.
摘要翻译：在HVDC功率转换器的领域中，需要一种改进的半导体开关电路，其消除了与表现出不同性能特征的各个半导体开关元件相关联的困难并且其性能具有固有的局限性。半导体开关电路（70; 80; 90）包括主电流分支（74; 92），其包括至少一个主半导体开关元件（12），并且当主或半主开半导体开关元件（12）接通。半导体开关电路（70; 80; 90）还包括与主电流分支（74; 92）并联连接的辅助电流分支（76; 104）。辅助电流分支（76; 104）包括至少一个辅助半导体开关元件（72），并且所述或每个辅助半导体开关元件（72）具有与其可操作地连接的控制单元（30）。所述或每个控制单元（30）被配置为当所述或每个主半导体开关元件（12）被接通时，在所述辅助电流支路（76; 104）中接通或辅助半导体开关元件（72），以选择性地产生经由辅助电流分支（76; 104）的替代电流路径（32; 108），由此通过主电流分支（74; 92）沿第一方向（D1）流动的电流被转向以流过替代电流路径（ 32; 108），以便在所述主半导体开关元件（12）接通之后立即降低流经所述主要半导体开关元件（12）的电流的变化率。

43. 发明申请

WO2014120398A1 AUTOMATIC BIPOLAR SIGNAL SWITCHING 审中-公开
标题翻译：自动双极信号切换
公开(公告)号：WO2014120398A1
公开(公告)日：2014-08-07
申请号：PCT/US2014/010640
申请日：2014-01-08
申请人： GENERAL ELECTRIC COMPANY
发明人： ABAWI, Daniel, Zahi , ROYLANCE, James, Merrill
IPC分类号： G01D3/024 , H03K5/08
CPC分类号： H03K17/16 , G01D3/024 , H03K5/082 , H03K17/161
摘要： A system is provided that includes an input node (2) configured to receive a signal (20) indicative of sensor data (fig. 1: 16). The system also includes a first transistor (48) configured to route the signal (20) to a positive channel (66) when a polarity of the signal is positive. Moreover, the system includes a second transistor (46) configured to route the signal to a negative channel (49) when a polarity of the signal (20) is negative. Additionally, the system includes the positive channel (34) coupled to the first transistor configured to route the signal to an analysis component (fig. 1: 24). Furthermore, the system includes the negative channel (49) coupled to the second transistor (46) and configured to route the signal to the analysis component (fig. 1: 24).
摘要翻译：提供了一种系统，其包括被配置为接收指示传感器数据的信号（20）的输入节点（2）（图1：16）。该系统还包括当信号的极性为正时被配置为将信号（20）路由到正通道（66）的第一晶体管（48）。此外，该系统包括第二晶体管（46），其被配置为当信号（20）的极性为负极时将信号路由到负通道（49）。另外，该系统包括耦合到第一晶体管的正通道（34），其被配置为将信号路由到分析部件（图1：24）。此外，该系统包括耦合到第二晶体管（46）并被配置为将信号路由到分析部件的负通道（49）（图1：24）。

44. 发明申请

WO2013085839A3 SEMICONDUCTOR MODULES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：半导体模块及其形成方法
公开(公告)号：WO2013085839A3
公开(公告)日：2013-09-26
申请号：PCT/US2012067569
申请日：2012-12-03
申请人： TRANSPHORM INC
发明人： WU YIFENG , YEA SUNG HAE
IPC分类号： H01L27/00 , H01L21/77
CPC分类号： H01L23/49838 , H01L21/56 , H01L23/3735 , H01L23/49811 , H01L23/49866 , H01L23/552 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/80 , H01L24/85 , H01L25/0655 , H01L25/0657 , H01L25/072 , H01L25/074 , H01L25/50 , H01L27/0629 , H01L27/0883 , H01L29/2003 , H01L29/7787 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/48091 , H01L2224/48105 , H01L2224/48137 , H01L2224/48145 , H01L2224/48249 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2225/06568 , H01L2924/00014 , H01L2924/10253 , H01L2924/1033 , H01L2924/12036 , H01L2924/13055 , H01L2924/13064 , H01L2924/13091 , H01L2924/30107 , H03K17/161 , H03K17/162 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.
摘要翻译：描述了电子模块以及模块的形成和操作方法。模块包括电容器，第一开关器件和第二开关器件。电子模块还包括诸如DBC衬底的衬底，其包括在第一金属层和第二金属层之间的绝缘层，并且可以包括彼此堆叠的多层DBC衬底。第一金属层包括通过在两个部分之间穿过第一金属层形成的沟槽彼此隔离的第一部分和第二部分。第一和第二开关器件在第一金属层之上，电容器的第一端子电连接到第一金属层的第一部分，并且电容器的第二端子电连接到第一金属的第二部分层，电容器在沟槽上延伸。

45. 发明申请

WO2013085839A2 SEMICONDUCTOR MODULES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：半导体模块及其形成方法
公开(公告)号：WO2013085839A2
公开(公告)日：2013-06-13
申请号：PCT/US2012/067569
申请日：2012-12-03
申请人： TRANSPHORM INC.
发明人： WU, Yifeng , YEA, Sung Hae
IPC分类号： H01L27/00 , H01L21/77
CPC分类号： H01L23/49838 , H01L21/56 , H01L23/3735 , H01L23/49811 , H01L23/49866 , H01L23/552 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/80 , H01L24/85 , H01L25/0655 , H01L25/0657 , H01L25/072 , H01L25/074 , H01L25/50 , H01L27/0629 , H01L27/0883 , H01L29/2003 , H01L29/7787 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/48091 , H01L2224/48105 , H01L2224/48137 , H01L2224/48145 , H01L2224/48249 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2225/06568 , H01L2924/00014 , H01L2924/10253 , H01L2924/1033 , H01L2924/12036 , H01L2924/13055 , H01L2924/13064 , H01L2924/13091 , H01L2924/30107 , H03K17/161 , H03K17/162 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.
摘要翻译：描述了电子模块，以及形成和操作模块的方法。该模块包括电容器，第一开关装置和第二开关装置。电子模块还包括诸如DBC基板的基板，其包括在第一金属层和第二金属层之间的绝缘层，并且可以包括彼此堆叠的多层DBC基板。第一金属层包括第一部分和第二部分，第一部分和第二部分通过穿过两部分之间的第一金属层形成的沟槽彼此隔离。第一开关装置和第二开关装置在第一金属层上方，电容器的第一端子电连接到第一金属层的第一部分，并且电容器的第二端子电连接到第一金属的第二部分层，电容器在沟槽上延伸。

46. 发明申请

WO2012123990A1 終端回路、半導体装置および試験システム审中-公开
标题翻译：终端电路，半导体器件和测试系统
公开(公告)号：WO2012123990A1
公开(公告)日：2012-09-20
申请号：PCT/JP2011/001540
申请日：2011-03-16
申请人：富士通株式会社 , 鈴木俊秀 , 川野陽一
发明人：鈴木俊秀 , 川野陽一
IPC分类号： H03H11/28 , G01R31/28 , H03H7/38 , H03K19/0175 , H04B1/04 , H04B3/02
CPC分类号： G01R31/3183 , G01R31/2822 , H03F1/56 , H03F2200/387 , H03H11/30 , H03K17/161 , H04B1/0458 , H04L25/0278 , H04L25/0298
摘要：　終端回路は、ｐＭＯＳトランジスタ、インダクタおよびキャパシタを含んでいる。ｐＭＯＳトランジスタは、伝送信号を出力または入力する信号端子にソースが接続され、ドレインが接地線に接続され、ゲートで制御信号を受け、特性インピーダンスの整合機能を有効にするときにオンされ、整合機能を無効にするときにオフされる。インダクタおよびキャパシタは、特性インピーダンスを整合するために、信号端子に接続される。ｐＭＯＳトランジスタを制御信号によりオンまたはオフすることで、終端回路による特性インピーダンスの整合機能を有効または無効に切り替えできる。これにより、例えば、外付けの終端抵抗を接続することなく、終端抵抗が付いた状態を実現でき、伝送信号の出力端子での信号レベルをモニタすることが可能になる。
摘要翻译：端子电路包括pMOS晶体管，电感器和电容器。 pMOS晶体管的源极连接到输出或作为输入接收发送信号的信号端子，其漏极连接到地线，并且与栅极接收控制信号。当整流功能无效时，当整流特性阻抗的功能有效时，pMOS晶体管导通。电感器和电容器连接到信号端子，以便整流特性阻抗。通过控制信号来打开或关闭pMOS晶体管可以将端子电路的特性阻抗整流功能切换到有源或无效。因此，例如可以实现终端电阻器就位的状态，并且在不连接外部端子电阻的情况下监视输出端子处的发送信号的信号电平。

47. 发明申请

WO2011089808A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2011089808A1
公开(公告)日：2011-07-28
申请号：PCT/JP2010/072839
申请日：2010-12-14
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , TAKEMURA, Yasuhiko , YAMAZAKI, Shunpei
发明人： TAKEMURA, Yasuhiko , YAMAZAKI, Shunpei
IPC分类号： H03K19/177 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L27/092 , H01L29/786
CPC分类号： H03K19/0013 , H01L27/0629 , H01L29/7869 , H01L2924/0002 , H03K17/161 , H03K19/173 , H03K19/17724 , H03K19/17736 , H03K19/1776 , H03K19/17772 , H03K19/17784 , H01L2924/00
摘要： It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.
摘要翻译：本发明的目的是提供能够降低功耗的半导体装置。另一个目的是提供使用诸如可编程逻辑器件（PLD）之类的编程单元的高度可靠的半导体器件。根据基本块之间的连接配置的变化，改变基本块的供电电压。也就是说，当基本块之间的连接结构使得基本块不对电路有贡献时，停止向该基本块提供电源电压。此外，使用使用使用氧化物半导体形成沟道形成区域的场效应晶体管形成的编程单元来控制对基本块的电源电压的供给，场效应晶体管具有极低的截止电流或极低漏电流。

48. 发明申请

WO2011088853A1 TRANSMISSION CHANNEL, IN PARTICULAR FOR ULTRASOUND APPLICATIONS 审中-公开
标题翻译：传输通道，特别是超声波应用
公开(公告)号：WO2011088853A1
公开(公告)日：2011-07-28
申请号：PCT/EP2010/005927
申请日：2010-09-29
申请人： STMICROELECTRONICS S.R.L. , ROSSI, Sandro , RICOTTI, Giulio , GHISU Davide Ugo , RICCIARDO, Antonio
发明人： ROSSI, Sandro , RICOTTI, Giulio , GHISU Davide Ugo , RICCIARDO, Antonio
IPC分类号： H03K17/06 , H03K17/687 , H03K17/74 , B06B1/02 , H03K17/0416 , H03K17/16
CPC分类号： H03K17/06 , H03K17/04163 , H03K17/161 , H03K17/6872 , H03K17/74
摘要： A transmission channel (1) is described comprising at least one high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVP0, HVP1, HVM0, HVM1), a clamping circuit (10) being connected to a first output terminal (HVout) of the transmission channel (1), an antinoise block (6) being connected between the first output terminal (HVout) and a connection terminal (Xdcr) of the transmission channel (1); as well as a switching circuit (30) being inserted between the connection terminal (Xdcr) and a second output terminal (LVout) of the transmission channel (1). Advantageously according to the invention, the clamping circuit (10) comprises a clamping core (11), a reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4 ) inserted between circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) of the high voltage buffer block (4) and of the clamping circuit (10), the circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2 ) being in correspondance with conduction terminals of said transistors (MB1,MB2,MB3,MB4,MC1,MC2) comprised into the high voltage buffer block(4) and into the clamping circuit (10), and a switching circuit (30).
摘要翻译：描述了传输通道（1），其包括至少一个包括缓冲晶体管（MB1，MB2，MB3，MB4）和相应的缓冲二极管（DB1，DB2，DB3，DB4）的高压缓冲块（4）参考（HVP0，HVP1，HVM0，HVM1），与传输通道（1）的第一输出端子（HVout）连接的钳位电路（10），连接在第一输出端子）和传输信道（1）的连接终端（Xdcr）; 以及插入在传输通道（1）的连接端子（Xdcr）和第二输出端子（LVout）之间的开关电路（30）。有利地，根据本发明，夹紧电路（10）包括夹紧芯（11），复位电路（20），其包括插入在电路节点（XME1，XME2，XME3，XME4，XME3，DME3，高电压缓冲块（4）和钳位电路（10）的电路节点（XME1，XME2，XME3，XME4，XC1，XC2）与所述晶体管（MB1，XC1，XC2）的导通端子相对应， MB2，MB3，MB4，MC1，MC2）以及开关电路（30），其特征在于，包括高压缓冲块（4）和钳位电路（10）。

49. 发明申请

WO2011046015A1 LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：逻辑电路和半导体器件
公开(公告)号：WO2011046015A1
公开(公告)日：2011-04-21
申请号：PCT/JP2010/066745
申请日：2010-09-21
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , YAMAZAKI, Shunpei , KOYAMA, Jun , TSUBUKU, Masashi , NODA, Kosei
发明人： YAMAZAKI, Shunpei , KOYAMA, Jun , TSUBUKU, Masashi , NODA, Kosei
IPC分类号： H03K19/0175 , G09G3/20 , G09G3/30 , G09G3/36 , H01L29/786 , H03K19/094 , H03K19/0952 , H03K19/096 , H03K23/44
CPC分类号： H01L27/1255 , G09G3/20 , G09G3/2092 , G09G3/3233 , G09G3/3291 , G09G3/36 , G09G3/3648 , G09G2300/0439 , G09G2300/08 , G09G2300/0842 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/08 , G11C19/184 , G11C19/28 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L29/7869 , H03K17/161 , H03K19/00315 , H03K19/096
摘要： To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1 x10 -13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
摘要翻译：为了减小晶体管的漏电流，可以抑制逻辑电路的故障。逻辑电路包括晶体管，其包括具有沟道形成层的功能的氧化物半导体层，并且其中截止电流在沟道宽度中每微米为1×10 -13A或更小。作为时钟信号的第一信号，第二信号和第三信号被输入作为输入信号。作为输出信号输出第四信号和第五信号，其电压状态根据输入的第一至第三信号而被设定。

50. 发明申请

WO2009084269A1 半導体装置及び表示装置审中-公开
标题翻译：半导体器件和显示器件
公开(公告)号：WO2009084269A1
公开(公告)日：2009-07-09
申请号：PCT/JP2008/064782
申请日：2008-08-20
申请人：シャープ株式会社 , 山本悦雄 , 佐々木寧 , 村上祐一郎 , 古田成
发明人：山本悦雄 , 佐々木寧 , 村上祐一郎 , 古田成
IPC分类号： H03K17/06 , G02F1/133 , G09G3/20 , G09G3/36 , H03K17/00 , H03K17/687
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2310/0289 , G11C19/28 , H01L27/124 , H03K17/161 , H03K17/162 , H03K17/687
摘要：　ｎチャネル型の複数のトランジスタにより構成される回路（１０）は、ドレイン端子に入力信号が入力され、ソース端子から出力信号が出力されるトランジスタ（Ｔ１）と、ドレイン端子に制御信号（Ｄ）が入力され、ソース端子がトランジスタ（Ｔ１）のゲート端子に接続されるトランジスタ（Ｔ２）とを備えている。トランジスタ（Ｔ２）のゲート端子と、トランジスタ（Ｔ２）のソース端子とは互いに接続されている。これにより、同一導電型のトランジスタからなり、ノイズの影響を低減することができる半導体装置、及びそれを備えた表示装置を提供する。
摘要翻译：由多个n沟道晶体管构成的电路（10）包括晶体管（T1），其中输入信号被输入到漏极端子，并且输出信号从源极端子和晶体管（T2）输出，其中，控制信号（D）输入到漏极端子，其源极端子连接到晶体管（T1）的栅极端子。晶体管（T2）的栅极端子和晶体管（T2）的源极端子彼此连接。因此，提供由相同并且不受噪声影响的导电型晶体管和包括它的显示装置组成的半导体器件。

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