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21. 发明申请

WO2018125493A1 PROGRAMMABLE REDISTRIBUTION DIE 审中-公开
公开(公告)号：WO2018125493A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/063727
申请日：2017-11-29
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , LIM, Min Suet , TEH, J-Wing , CHEAH, Bok Eng
IPC分类号： H01L25/065 , H01L25/07 , H01L23/12 , H01L23/00 , H01L23/485
摘要： A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.

22. 发明申请

WO2018111512A1 PACKAGE-BOTTOM INTERPOSERS FOR LAND-SIDE CONFIGURED DEVICES FOR SYSTEM-IN-PACKAGE APPARATUS 审中-公开
公开(公告)号：WO2018111512A1
公开(公告)日：2018-06-21
申请号：PCT/US2017/062741
申请日：2017-11-21
申请人： INTEL CORPORATION
发明人： LOO, Howe Yin , GOH, Eng Huat , LIM, Min Suet , CHEAH, Bok Eng , KONG, Jackson Chung Peng , YONG, Khang Choong
IPC分类号： H01L25/065 , H01L23/00
摘要： A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a package bottom interposer disposed on the package substrate on a land side. A land side board mates with the package bottom interposer, and enough vertical space is created by the package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.

23. 发明申请

WO2018111471A1 MICROELECTRONIC DEVICE HAVING AN AIR CORE INDUCTOR 审中-公开
公开(公告)号：WO2018111471A1
公开(公告)日：2018-06-21
申请号：PCT/US2017/061128
申请日：2017-11-10
申请人： INTEL CORPORATION
发明人： CHEAH, Bok Eng , KONG, Jackson Chung Peng , YONG, Khang Choong , LIM, Min Suet , KUAN, Chin Lee , LOO, Howe Yin
IPC分类号： H01L23/64 , H01L23/522 , H01L25/07
摘要： A microelectronic device incorporating an air core inductor having one or more inserts to provide efficiency of the inductor are described. One or more inserts having a selected permeability may be placed within regions defined by coils of the air core inductor. The inserts can be formed of a solid material of the selected permeability or such a material can be applied to other structures, such as circuit components. Other embodiments may be described and/or claimed.

24. 发明申请

WO2018063655A1 MICROELECTRONIC DEVICE PACKAGE ELECTROMAGNETIC SHIELD 审中-公开
标题翻译：微电子器件包装电磁屏蔽
公开(公告)号：WO2018063655A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049012
申请日：2017-08-29
申请人： INTEL CORPORATION
发明人： LIM, Min Suet , GOH, Eng Huat , YONG, Khang Choong , KOH, Boon Ping , SONG, Wil Choon
IPC分类号： H01L23/60 , H01L23/485 , H01L23/00 , H01L25/07
CPC分类号： G06F1/182 , H01L23/552 , H01L24/16 , H01L24/33 , H01L2224/16237 , H01L2924/14 , H01L2924/1434 , H01L2924/15313 , H01L2924/3025
摘要： Microelectronic devices including an electromagnetic shield over a desired portion of a substrate. The magnetic shield is formed of conductive particles within a selectively curable layer, such as a solder resist material. After application to the substrate, the conductive particles are allowed to settle to form a conductive structure to serve as an electromagnetic shield. The electromagnetic shield can be formed primarily over regions of the substrate containing conductive traces coupled in the package to communicate signals presenting a risk of causing electromagnetic interference with other devices.
摘要翻译：包括在衬底的期望部分上的电磁屏蔽的微电子器件。磁屏蔽由选择性可固化层内的导电颗粒形成，例如阻焊材料。在施加到衬底之后，允许导电颗粒沉降以形成导电结构以用作电磁屏蔽。电磁屏蔽可以主要形成在包含耦合在封装中的导电迹线的基板的区域上，以传递具有引起对其他设备的电磁干扰的风险的信号。

25. 发明申请

WO2018052413A1 SEMICONDUCTOR PACKAGE HAVING INTEGRATED STIFFENER REGION 审中-公开
标题翻译：半导体封装具有集成加速器区域
公开(公告)号：WO2018052413A1
公开(公告)日：2018-03-22
申请号：PCT/US2016/051697
申请日：2016-09-14
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , SIR, Jiun Hann , LIM, Min Suet , LIFF, Shawna M. , EID, Feras
IPC分类号： H01L23/00 , H01L23/552 , H01L23/498 , H01L23/538
摘要： Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.
摘要翻译：提供缓解封装衬底的翘曲和/或其他类型或机械变形的半导体封装。在一些实施例中，封装衬底可以包括具有诸如金属层，金属互连或其组合的刚性导电构件的组件的外围导电区域。在制造封装衬底的过程中，外围导电区域可以被集成到封装衬底中。在一些实施方式中，光刻定义的导电构件可以被杠杆化以形成延伸的导电层，与几乎圆柱形的导电通孔相比，延伸的导电层可以提供增加的刚度。非外围导电区域也可以集成到半导体封装中以便减少机械变形的特定图案和/或提供其他功能，例如电磁干扰（EMI）屏蔽。

26. 发明申请

WO2018009291A1 SUBSTRATE WITH SUB-INTERCONNECT LAYER 审中-公开
标题翻译：具有子互连层的基板
公开(公告)号：WO2018009291A1
公开(公告)日：2018-01-11
申请号：PCT/US2017/035838
申请日：2017-06-02
申请人： INTEL CORPORATION
发明人： GOH, Eng Huet , SIR, Jiun Hann , LIM, Min Suet , YONG, Khang Choong
IPC分类号： H01L23/498 , H01L21/48 , H01L23/538
摘要： Electrical interconnect technology for a package substrate is disclosed. A substrate can include a first conductive element at least partially disposed in a first routing layer, and a second conductive element at least partially disposed in a second routing layer. The first and second routing layers are adjacent routing layers. The substrate can also include a third conductive element having first and second portions disposed in the first routing layer, and an intermediate third portion disposed in a "sub-interconnect layer" between the first and second routing layers.
摘要翻译：公开了用于封装衬底的电互连技术。衬底可以包括至少部分地设置在第一布线层中的第一导电元件以及至少部分布置在第二布线层中的第二导电元件。第一和第二路由层是相邻的路由层。衬底还可以包括具有设置在第一布线层中的第一和第二部分的第三导电元件以及设置在“子互连层”中的中间第三部分。在第一和第二路由层之间。

27. 发明申请

WO2017052751A1 SUBSTRATE INCLUDING STRUCTURES TO COUPLE A CAPACITOR TO A PACKAGED DEVICE AND METHOD OF MAKING SAME 审中-公开
标题翻译：包含用于将电容器耦合到包装器件的结构的衬底及其制造方法
公开(公告)号：WO2017052751A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/044076
申请日：2016-07-26
申请人： INTEL CORPORATION
发明人： CHUAH, Tin Poay , LIM, Min Suet , OOI, Ping Ping , GOH, Eng Huat , CHOW, See Chin
IPC分类号： H05K3/34 , H01L23/488 , H01L23/498
CPC分类号： H05K1/183 , H01L2224/14 , H05K1/0231 , H05K1/113 , H05K1/141 , H05K1/181 , H05K3/4697 , H05K2201/10015 , H05K2201/10159 , H05K2201/10734
摘要： Techniques and mechanisms to provide interconnect structures of a substrate such as a printed circuit board. In an embodiment, a first side of a substrate has disposed thereon a hardware interface contacts to couple the substrate to a packaged IC device. The contacts define a footprint area, where an overlap region of the substrate is defined by a projection of the footprint area from the first side to a second side of the substrate. The substrate forms a recess extending from one of the first side and the second side. In another embodiment, at least part of the recess is within the overlap region, and interconnect structures of the substrate facilitate connection between the packaged IC device and a capacitor disposed at least partially in the recess. Positioning of the capacitor within the overlap region enables improvements in substrate space efficiency, power delivery and/or signal noise.
摘要翻译：提供诸如印刷电路板的基板的互连结构的技术和机构。在一个实施例中，衬底的第一侧上设置有将衬底耦合到封装的IC器件的硬件接口触点。触点限定了覆盖区域，其中衬底的重叠区域由衬底的第一侧到第二侧的覆盖区域的投影来限定。衬底形成从第一侧和第二侧中的一个延伸的凹部。在另一个实施例中，凹槽的至少一部分在重叠区域内，并且衬底的互连结构便于封装的IC器件与至少部分地设置在凹槽中的电容器之间的连接。电容器在重叠区域内的定位能够改善衬底空间效率，功率传递和/或信号噪声。

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