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1. 发明申请

WO2018009166A1 COMBINATION STIFFENER AND CAPACITOR 审中-公开
标题翻译：组合加长器和电容器
公开(公告)号：WO2018009166A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040906
申请日：2016-07-02
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , SIR, Jiun Hann , LIM, Min Suet
IPC分类号： H01L23/16
CPC分类号： H01L23/16 , H01L24/16 , H01L24/48 , H01L25/16 , H01L2224/131 , H01L2224/16227 , H01L2224/48227 , H01L2924/1433 , H01L2924/1434 , H01L2924/15192 , H01L2924/16251 , H01L2924/19041 , H01L2924/19105 , H01L2924/014 , H01L2924/00014
摘要： Electronic device package stiffener and capacitor technology is disclosed. A combination stiffener and capacitor can include a structural material configured to be coupled to a substrate. The structural material can have a shape configured to provide mechanical support for the substrate. The combination stiffener and capacitor can also include first and second electrodes forming a capacitor. An electronic device package and a package substrate configured to receive the combination stiffener and capacitor are also disclosed.
摘要翻译：公开了电子器件封装加强件和电容器技术。组合加强件和电容器可以包括被配置为耦合到衬底的结构材料。结构材料可以具有被配置成为基板提供机械支撑的形状。组合加强件和电容器还可以包括形成电容器的第一和第二电极。还公开了配置成接收组合加强件和电容器的电子器件封装和封装衬底。

2. 发明申请

WO2018004850A1 SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING A PAD ON SOLDER MASK (POSM) SEMICONDUCTOR SUBSTRATE PACKAGE 审中-公开
标题翻译：用于在焊料掩模（POSM）半导体衬底封装上实施焊盘的系统，方法和设备
公开(公告)号：WO2018004850A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/032938
申请日：2017-05-16
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , SIR, Jiun Hann , LIM, Min Suet
IPC分类号： H01L23/00 , H01L23/498 , H01L23/31
摘要： In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.
摘要翻译：根据所公开的实施例，提供了用于实现焊盘上焊盘（PoSM）半导体衬底封装的系统，方法和设备。例如，根据一个实施例，存在一种衬底封装，其中在衬底封装的顶层处实现了功能硅芯片; 位于衬底封装的功能硅芯片下方的阻焊层; 在所述功能硅管芯的底表面处的多个管芯凸块，所述多个管芯凸块通过所述阻焊层的顶表面处的多个焊球将所述功能硅管芯与衬底电连接; 所述多个裸片凸块中的每一个至少部分地在所述阻焊层内并且在所述焊球下方电连接到镍垫; 多个管芯凸块中的每一个通过镍焊盘电连接到暴露在阻焊层的底表面处的导电焊盘; 并且其中暴露在阻焊层的底表面处的每个导电焊盘与在衬底封装的衬底处的电迹线电接口。披露了其他相关的实施例。

3. 发明申请

WO2017099931A1 REDUCED-HEIGHT MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：减小高度存储器系统和方法
公开(公告)号：WO2017099931A1
公开(公告)日：2017-06-15
申请号：PCT/US2016/061043
申请日：2016-11-09
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , LIM, Min Suet , SIR, Jiun Hann
IPC分类号： H01L23/31 , H01L23/00 , H01L23/498
CPC分类号： H01L25/0657 , H01L23/3128 , H01L25/105 , H01L25/18 , H01L25/50 , H01L27/108 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/0652 , H01L2225/06548 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/1815 , H01L2924/18161 , H01L2924/00014
摘要： A computer memory module can include a molded layer disposed on a DRAM substrate. The molded layer can encapsulate a DRAM die and wire bonds that connect the DRAM die to the DRAM substrate, and can be shaped to include at least one cavity having a footprint sized to accommodate a system on chip (SOC) die. The DRAM module can attach to an SOC package so that the SOC die and the DRAM die are both positioned between the DRAM substrate and the SOC package, the DRAM substrate can form its electrical connections on only one side of the DRAM substrate, and the SOC die can fit at least partially into the cavity in the molded layer. This can reduce a package Z-height, compared to conventional DRAM packages in which the SOC die and the DRAM die are positioned on opposite sides of the DRAM substrate.
摘要翻译：计算机存储器模块可以包括设置在DRAM基板上的模制层。模制层可以封装DRAM管芯和将DRAM管芯连接至DRAM衬底的引线接合，并且可以被成形为包括至少一个具有尺寸适合于容纳片上系统（SOC）管芯的覆盖区的空腔。 DRAM模块可以连接到SOC封装，使得SOC裸片和DRAM裸片都位于DRAM衬底和SOC封装之间，DRAM衬底可以仅在DRAM衬底的一侧形成其电连接，并且SOC 模具可以至少部分地配合到模制层中的空腔中。与其中SOC裸片和DRAM裸片位于DRAM衬底的相对侧上的常规DRAM封装相比，这可以减小封装Z高度。

4. 发明申请

WO2018063632A1 THREE CAPACITOR STACK AND ASSOCIATED METHODS 审中-公开
标题翻译：三个电容堆叠和相关方法
公开(公告)号：WO2018063632A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/048824
申请日：2017-08-28
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , SIR, Jiun Hann , CHUA, Han Kung , LIM, Min Suet , TEOH, Hoay Tien
IPC分类号： H01G4/38 , H01G4/30
CPC分类号： H01L28/75
摘要： A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.
摘要翻译：显示了三个电容器堆叠和相关的方法。示例性电容器装置可以包括：第一电容器叠层，其包括与第一电容器电极交错的第一多个参考电极层;第一电容器叠层上的第二电容器叠层，其包括与第二电容器电极交错的第二多个参考电极层以及在第二电容器堆叠上的第三电容器堆叠，其包括参考电极和第三电容器电极。在参考电极和第一电容器电极，第二电容器电极和第三电容器电极之间形成相应的介电材料层。

5. 发明申请

WO2018009168A1 ELECTRONIC DEVICE PACKAGE ON PACKAGE (POP) 审中-公开
标题翻译：电子设备包装（POP）
公开(公告)号：WO2018009168A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040908
申请日：2016-07-02
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , SIR, Jiun Hann , LIM, Min Suet , GUO, Xi
IPC分类号： H01L25/10 , H01L25/18 , H01L23/367
摘要： Electronic device package on package (POP) technology is disclosed. A POP can comprise a first electronic device package including a heat source. The POP can also comprise a second electronic device package disposed on the first electronic device package. The second electronic device package can include a substrate having a heat transfer portion proximate the heat source that facilitates heat transfer from the heat source through a thickness of the substrate. The substrate can also have an electronic component portion at least partially about the heat transfer portion that facilitates electrical communication. In addition, the POP can comprise an electronic component operably coupled to the electronic component portion.
摘要翻译：公开了电子装置封装（POP）技术。 POP可以包括包含热源的第一电子设备包。 POP还可以包括设置在第一电子设备包上的第二电子设备包。第二电子器件封装可以包括具有靠近热源的传热部分的基板，其有助于从热源通过基板厚度的热传递。衬底还可以具有电子组件部分，该电子组件部分至少部分地围绕促进电通信的传热部分。另外，POP可以包括可操作地耦合到电子组件部分的电子组件。

6. 发明申请

WO2017218135A1 CAPACITIVE INTERCONNECT IN A SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：半导体封装中的容性互连
公开(公告)号：WO2017218135A1
公开(公告)日：2017-12-21
申请号：PCT/US2017/033340
申请日：2017-05-18
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , LIM, Min Suet , TAN, Fern Nee , YONG, Khang Choong , SIR, Jiun Hann
IPC分类号： H01L23/495 , H01L23/498 , H01L23/00 , H01L25/07 , H01L49/02
摘要： Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.
摘要翻译：提供用于制造电容互连的电容互连和工艺。在一些实施例中，电容性互连件包括第一金属层，第二金属层; 以及介电层，其包括插入第一金属层的第一金属层和第二金属层的第二金属层的介电层。这些层可以以几乎同心的结构组装，其中电介质层邻接第一金属层并且第二金属层邻接电介质层。另外，电容性互连可以包括电耦合到第一金属层中的至少一个的第一电极和电耦合到第二金属层中的至少一个的第二电极，第二电极与第一电极相对组装。第一电极和第二电极可以包括各自的焊料顶部。

7. 发明申请

WO2018052413A1 SEMICONDUCTOR PACKAGE HAVING INTEGRATED STIFFENER REGION 审中-公开
标题翻译：半导体封装具有集成加速器区域
公开(公告)号：WO2018052413A1
公开(公告)日：2018-03-22
申请号：PCT/US2016/051697
申请日：2016-09-14
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , SIR, Jiun Hann , LIM, Min Suet , LIFF, Shawna M. , EID, Feras
IPC分类号： H01L23/00 , H01L23/552 , H01L23/498 , H01L23/538
摘要： Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.
摘要翻译：提供缓解封装衬底的翘曲和/或其他类型或机械变形的半导体封装。在一些实施例中，封装衬底可以包括具有诸如金属层，金属互连或其组合的刚性导电构件的组件的外围导电区域。在制造封装衬底的过程中，外围导电区域可以被集成到封装衬底中。在一些实施方式中，光刻定义的导电构件可以被杠杆化以形成延伸的导电层，与几乎圆柱形的导电通孔相比，延伸的导电层可以提供增加的刚度。非外围导电区域也可以集成到半导体封装中以便减少机械变形的特定图案和/或提供其他功能，例如电磁干扰（EMI）屏蔽。

8. 发明申请

WO2018009291A1 SUBSTRATE WITH SUB-INTERCONNECT LAYER 审中-公开
标题翻译：具有子互连层的基板
公开(公告)号：WO2018009291A1
公开(公告)日：2018-01-11
申请号：PCT/US2017/035838
申请日：2017-06-02
申请人： INTEL CORPORATION
发明人： GOH, Eng Huet , SIR, Jiun Hann , LIM, Min Suet , YONG, Khang Choong
IPC分类号： H01L23/498 , H01L21/48 , H01L23/538
摘要： Electrical interconnect technology for a package substrate is disclosed. A substrate can include a first conductive element at least partially disposed in a first routing layer, and a second conductive element at least partially disposed in a second routing layer. The first and second routing layers are adjacent routing layers. The substrate can also include a third conductive element having first and second portions disposed in the first routing layer, and an intermediate third portion disposed in a "sub-interconnect layer" between the first and second routing layers.
摘要翻译：公开了用于封装衬底的电互连技术。衬底可以包括至少部分地设置在第一布线层中的第一导电元件以及至少部分布置在第二布线层中的第二导电元件。第一和第二路由层是相邻的路由层。衬底还可以包括具有设置在第一布线层中的第一和第二部分的第三导电元件以及设置在“子互连层”中的中间第三部分。在第一和第二路由层之间。

9. 发明申请

WO2016074176A1 FLEXIBLE SYSTEM-IN-PACKAGE SOLUTIONS FOR WEARABLE DEVICES 审中-公开
标题翻译：用于可穿戴设备的灵活的系统级封装解决方案
公开(公告)号：WO2016074176A1
公开(公告)日：2016-05-19
申请号：PCT/CN2014/090939
申请日：2014-11-12
申请人： INTEL CORPORATION , TANG, Jiamiao , ZHAO, Junfeng , SKINNER, Michael P. , SHE, Yong , SIR, Jiun Hann , CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , CHEW, Yen Hsiang
发明人： TANG, Jiamiao , ZHAO, Junfeng , SKINNER, Michael P. , SHE, Yong , SIR, Jiun Hann , CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , CHEW, Yen Hsiang
IPC分类号： H01L23/28
CPC分类号： G06F1/163 , A41B1/00 , A41D1/06 , A41D1/08 , A41F9/002 , A43B3/001 , A43B3/0015 , A43B7/141 , A44C5/0015 , A44C15/005 , F03G5/06 , G06F1/189 , H01L21/4853 , H01L21/565 , H01L23/3135 , H01L23/49838 , H01L23/4985 , H01L23/562 , H01L25/0655 , H01L25/50 , H01L2224/16225 , H01L2224/48091 , H01L2224/73257 , H01L2924/0002 , H01L2924/181 , H02J1/14 , H05K1/189 , H05K2201/05 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate (102). The flexible substrate (102) may have a plurality of dies (104 -112) coupled therewith. The IC package may include a first encapsulation material (116-120), having a first rigidity, disposed on the flexible substrate (102) to at least partially encapsulate each die of the plurality dies (104 -112). The IC package may further include a second encapsulation material (122), having a second rigidity, disposed on the flexible substrate (102). In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及集成电路（IC）封装。在实施例中，集成电路（IC）封装可以包括柔性基板（102）。柔性基板（102）可以具有与其连接的多个管芯（104-112）。 IC封装可以包括具有第一刚性的第一封装材料（116-120），其设置在柔性基板（102）上以至少部分地封装多个管芯（104-112）中的每个管芯。 IC封装还可以包括设置在柔性基板（102）上的具有第二刚性的第二封装材料（122）。在实施例中，第二刚性和第一刚度彼此不同。可以描述和/或要求保护其他实施例。

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