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121. 发明申请

WO2006073799A2 METHOD AND APPARATUS FOR CONTROLLING CHARGE TRANSFER IN CMOS SENSORS WITH AN IMPLANT BY THE TRANSFER GATE 审中-公开
标题翻译：用于控制通过转移门移植的CMOS传感器中的电荷转移的方法和装置
公开(公告)号：WO2006073799A2
公开(公告)日：2006-07-13
申请号：PCT/US2005046084
申请日：2005-12-20
申请人： ESS TECHNOLOGY INC , TOROS ZEYNEP , MANN RICHARD , BENCUYA SELIM
发明人： TOROS ZEYNEP , MANN RICHARD , BENCUYA SELIM
IPC分类号： H01L31/113
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/1463 , H01L27/14689
摘要： An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.
摘要翻译：公开了一种改进的CMOS传感器集成电路，以及制作电路的电路和计算机可读描述的方法。

122. 发明申请

WO2006044780A3 SCRAMBLING METHOD TO REDUCE WORDLINE COUPLING NOISE 审中-公开
标题翻译：减少WORDLINE耦合噪声的扫描方法
公开(公告)号：WO2006044780A3
公开(公告)日：2006-06-01
申请号：PCT/US2005037221
申请日：2005-10-17
申请人： TEXAS INSTRUMENTS INC , MADAN SUDHIR K
发明人： MADAN SUDHIR K
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： G11C11/22 , G11C5/063 , G11C8/14 , H01L27/11502
摘要： A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows and columns. Each row has a first part (1102) and a second part (1108). A first conductor is coupled to a respective column of memory cells in each first part. A second conductor is coupled to a respective column in each second part. A third conductor is coupled to a control terminal of each memory cell in the first part (1102) of a first row and the second part (1108) of a second row. In described embodiments, capacitive coupling is reduced by routing wordlines to limit the length proximity of adjacent logical wordlines.
摘要翻译：公开了一种用于减少由于字线耦合引起的阵列噪声的存储电路和方法。电路包括以行和列排列的多个存储单元。每排具有第一部分（1102）和第二部分（1108）。第一导体耦合到每个第一部分中的各个存储单元列。第二导体在每个第二部分中耦合到相应的列。第三导体耦合到第一行的第一部分（1102）中的每个存储器单元的控制端子和第二行的第二部分（1108）。在所描述的实施例中，通过路由字线来减小电容耦合以限制相邻逻辑字线的长度邻近。

123. 发明申请

WO2005112124A3 ISOLATION TRENCH 审中-公开
标题翻译：隔离开关
公开(公告)号：WO2005112124A3
公开(公告)日：2006-01-12
申请号：PCT/US2005011553
申请日：2005-04-05
申请人： FREESCALE SEMICONDUCTOR INC , YEAP CHOH-FEI , JEON YONGJOO , TURNER MICHAEL D , VAN GOMPEL TONI D
发明人： YEAP CHOH-FEI , JEON YONGJOO , TURNER MICHAEL D , VAN GOMPEL TONI D
IPC分类号： H01L21/302 , H01L21/461 , H01L21/76 , H01L21/762 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/00
CPC分类号： H01L21/76283 , H01L21/84
摘要： A process for forming an isolation trench (209) in a wafer (201). The process includes depositing (e.g. by a directional deposition process) a first dielectric material (307) in the trench (209) and then depositing a second dielectric material (309) (e.g. by a directional deposition process) over the first dielectric material (307) in the trench (209). A third material (501) is deposited in the trench (209) on the second dielectric material (309). The second material (309) and the third material (501) are selectively etchable with respect to each other. In one example, the first material (307) has a lower dielectric constant than the second material (309).
摘要翻译：一种用于在晶片（201）中形成隔离沟槽（209）的工艺。该方法包括在沟槽（209）中沉积（例如通过定向沉积工艺）第一介电材料（307），然后在第一介电材料（307）上沉积第二电介质材料（例如通过定向沉积工艺））在沟槽（209）中。第三材料（501）沉积在第二电介质材料（309）上的沟槽（209）中。第二材料（309）和第三材料（501）可相对于彼此可选择性地蚀刻。在一个示例中，第一材料（307）具有比第二材料（309）更低的介电常数。

124. 发明申请

WO2005117144A2 GATE DRIVER OUTPUT STAGE WITH BIAS CIRCUIT FOR HIGH AND WIDE OPERATING VOLTAGE RANGE 审中-公开
标题翻译：带宽偏置电路的门极驱动器输出级，用于高电平和大的工作电压范围
公开(公告)号：WO2005117144A2
公开(公告)日：2005-12-08
申请号：PCT/US2005/017273
申请日：2005-05-18
申请人： INTERNATIONAL RECTIFIER CORPORATION , JEONG, Jong-Deog
发明人： JEONG, Jong-Deog
IPC分类号： H01L31/113
CPC分类号： H03K19/00315 , H01L21/761 , H01L27/092
摘要： A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.
摘要翻译：一种简单，低成本的栅极驱动器和偏置电路提供了超过诸如NMOS和PMOS晶体管的组件的正常分量击穿电压的更宽的工作电压范围。在该示例中，使用具有外延层作为体积和p型衬底的CMOS工艺来实现电路。

125. 发明申请

WO2004053939A3 INTEGRATED CIRCUIT STRUCTURE WITH IMPROVED LDMOS DESIGN 审中-公开
标题翻译：集成电路结构与改进的LDMOS设计
公开(公告)号：WO2004053939A3
公开(公告)日：2005-07-21
申请号：PCT/US0338931
申请日：2003-12-09
申请人： FAIRCHILD SEMICONDUCTOR
发明人： CAI JUN
IPC分类号： H01L21/336 , H01L29/10 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/76 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7816 , H01L29/1095 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66689
摘要： A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced apart source regions (8) of a first conductivity type are formed in a portion of the layer between the pair of gate structures (2) with a first region of a second conductivity type formed there between. A lightly doped body region (6) of a second conductivity type is formed in the semiconductor layer, extending from below the source regions (8) to below the gate structures (2) and extending a variable depth into the semiconductor layer. This body region (6) is characterized by an inflection in depth in that portion of the body region extending below the first region.
摘要翻译：包括LDMOS器件结构的半导体集成电路包括在半导体层的上表面上的具有一对间隔开的场效应栅极结构的半导体层。第一导电类型的第一和第二间隔开的源极区（8）形成在一对栅极结构（2）之间的层的一部分中，其间形成有第二导电类型的第一区域。在半导体层中形成具有第二导电类型的轻掺杂体区域（6），从源极区域（8）的下方延伸到栅极结构（2）的下方，并将可变深度延伸到半导体层中。该身体区域（6）的特征在于在第一区域下方延伸的身体区域的部分中的深度变化。

126. 发明申请

WO2004088717A2 SUPERJUNCTION DEVICE AND METHOD OF MANUFACTURE THEREFORE 审中-公开
标题翻译：超级设备及其制造方法
公开(公告)号：WO2004088717A2
公开(公告)日：2004-10-14
申请号：PCT/US2004009164
申请日：2004-03-25
申请人： INT RECTIFIER CORP , HENSON TIMOTHY , CAO JIANJUN , SPRING KYLE
发明人： HENSON TIMOTHY , CAO JIANJUN , SPRING KYLE
IPC分类号： H01L20060101 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/78 , H01L31/062 , H01L31/113 , H01L
CPC分类号： H01L29/0634 , H01L29/1095 , H01L29/7813
摘要： A process for forming a superjunction device that includes a series of implants to form closely spaced implant regions which are linked together by a short thermal step, whereby deep and narrow regions can be formed within a semiconductor body.
摘要翻译：一种用于形成超级结装置的方法，其包括一系列植入物，以形成紧密间隔的注入区域，其通过短的热步骤连接在一起，由此可以在半导体主体内形成深和窄的区域。

127. 发明申请

WO03019671A3 VERTICAL DUAL GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：垂直双门场效应晶体管
公开(公告)号：WO03019671A3
公开(公告)日：2003-04-10
申请号：PCT/US0228265
申请日：2002-08-29
申请人： IBM
发明人： FURUKAWA TOSHIHARU , HAKEY MARK C , HOLMES STEVEN J , HORAK DAVID V , LEAS JAMES M , MA WILLIAM H L , RABIDOUX PAUL A
IPC分类号： H01L21/336 , H01L21/60 , H01L21/8234 , H01L27/088 , H01L29/78 , H01L29/786 , H01L29/76 , H01L21/3205 , H01L21/4763 , H01L21/8238 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/78642 , H01L21/2255 , H01L21/76897 , H01L21/823487 , H01L27/088 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A vertical transistor particularly suitable for high density integration includes potentially independent gate structures (3230) o opposite sides of a semiconductor pillar (2910) formed by etching in a trench. The gate structure is surrounded by insulting material (2620) which is selectively etchable to isolation material surrounding the transistor. A contact (3820) is made to the lower end of the pillar by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap (2730) and sidewalls of selectively etchable materials so that gate and source connection openings (3720, 3620) can also be made by selective etching with good registration tolerance.
摘要翻译：特别适用于高密度集成的垂直晶体管包括通过在沟槽中蚀刻形成的半导体柱（2910）的相对侧的潜在独立的栅极结构（3230）。栅极结构由绝缘材料（2620）包围，其被选择性地蚀刻到围绕晶体管的隔离材料。通过选择性地蚀刻对绝缘材料有选择性的隔离材料，将一个触点（3820）制成在支柱的下端。柱的上端由盖（2730）和选择性可蚀刻材料的侧壁覆盖，使得栅极和源极连接开口（3720,3620）也可以通过具有良好配准公差的选择性蚀刻制成。

128. 发明申请

WO02080287A2 SEMICONDUCTOR STRUCTURES AND DEVICES FOR DETECTING FAR-INFRARED LIGHT 审中-公开
标题翻译：用于检测红外光的半导体结构和器件
公开(公告)号：WO02080287A2
公开(公告)日：2002-10-10
申请号：PCT/US0148088
申请日：2001-12-10
申请人： MOTOROLA INC
发明人： DROOPAD RAVINDRANATH
IPC分类号： H01L21/20 , H01L21/36 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/09 , H01L31/101 , H01L31/113 , H01L31/119 , H01L31/18 , H01L33/00
CPC分类号： H01L31/1852 , H01L21/0237 , H01L21/02381 , H01L21/02439 , H01L21/02488 , H01L21/02507 , H01L21/0251 , H01L21/02521 , H01L31/1836 , H01L33/0066 , Y02E10/544 , Y02P70/521
摘要： High-quality epitaxial layers of narrow-bandgap monocrystalline semiconductor materials can be grown overlying monocrystalline substrates (22), such as large silicon wafers, by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing a monocrystalline oxide layer (24) on a silicon wafer. The oxide layer may be spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high-quality monocrystalline oxide layer. The oxide layer (24) is lattice-matched to both the underlying silicon wafer and the overlying monocrystalline semiconductor material layer (26). Any lattice mismatch between the oxide layer (24) and the underlying silicon substrate (22) is relieved by the amorphous interface layer (28). Optical structures, such as far-infrared detectors and emitters, can be grown on high-quality, epitaxial, narrow-bandgap compound semiconductor materials to create highly reliable devices at reduced costs.
摘要翻译：通过形成用于生长单晶层的柔性衬底，可以将窄带隙单晶半导体材料的高质量外延层生长成覆盖在单晶衬底（22）上，例如大的硅晶片。实现顺应性衬底的形成的一种方式包括首先在硅晶片上生长单晶氧化物层（24）。氧化物层可以通过氧化硅的非晶界面层（28）与硅晶片间隔开。非晶界面层（28）耗散应变并允许高质量单晶氧化物层的生长。氧化物层（24）与下面的硅晶片和上覆单晶半导体材料层（26）晶格匹配。氧化物层（24）和下面的硅衬底（22）之间的任何晶格失配被非晶界面层（28）释放。光学结构，例如远红外线检测器和发射器，可以在高品质，外延，窄带隙化合物半导体材料上生长，以降低成本创建高可靠性的器件。

129. 发明申请

WO0219389A3 EPITAXIAL TEMPLATE AND BARRIER FOR THE INTEGRATION OF FUNCTIONAL THIN FILM HETEROSTRUCTURES ON SILICON 审中-公开
标题翻译：用于在硅上集成功能薄膜异质结构的外延模板和屏障
公开(公告)号：WO0219389A3
公开(公告)日：2002-08-15
申请号：PCT/US0127050
申请日：2001-08-30
申请人： UNIV MARYLAND , PENN STATE RES FOUND
发明人： RAMESH RAMAMOORTHY , SCHLOM DARRELL G
IPC分类号： G11C11/22 , H01L20060101 , H01L21/02 , H01L21/285 , H01L21/8246 , H01L27/115 , H01L29/12 , H01L29/51 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28568 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： A ferroelectric memory cell formed on a monocrystalline silicon underlayer (60), either an epitaxial silicon contact plug to a transistor source or drain or silicon gate region for which the memory cell forms a non-volatile gate. A conductive barrier layer (62) of doped strontium titanate, whether cationically substituted, such by lanthanum or niobium for strontium and titanium respectively, or anionically deficient, is epitaxially grown over the silicon, and a lower metal oxide electrode layer (64) a ferroelectric layer (64) and an upper metal oxide electrode layer (68) are epitaxially grown on the barrier layer. No platinum barrier is needed beneath the ferroelectric stack. The invention can be applied to many other functional oxide devices including micromachined electromechanical (MEM) devices and ferromagnetic tri-layer devices.
摘要翻译：一种形成在单晶硅下层（60）上的铁电存储单元，或者是外延硅接触插塞到晶体管源极或漏极或硅栅极区域，存储单元形成非易失性栅极。掺杂的钛酸锶的导电阻挡层（62），不管是阳离子取代的，例如分别由镧或铌代替锶和钛，或阴离子缺陷，在硅上外延生长，下部金属氧化物电极层（64）层（64）和上金属氧化物电极层（68）在阻挡层上外延生长。在铁电堆栈下面不需要铂阻挡层。本发明可以应用于许多其他功能氧化物器件，包括微机械机电（MEM）器件和铁磁三层器件。

130. 发明申请

WO0068997A9 MOSFET WITH FIELD REDUCING TRENCHES IN BODY REGION 审中-公开
标题翻译： MOSFET在场地减少现场
公开(公告)号：WO0068997A9
公开(公告)日：2002-07-18
申请号：PCT/US0012191
申请日：2000-05-05
申请人： C P CLARE CORP
发明人： NEILSON JOHN M S , ZAFRANI MAXIME , POLCE NESTORE , JONES SCOTT
IPC分类号： H01L29/06 , H01L29/10 , H01L29/78 , H01L29/00 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/408 , H01L29/0634 , H01L29/0649 , H01L29/1095 , H01L29/7802
摘要： A MOSFET device (100) that exhibits low power loss characteristics by minimizing source-to-drain channel on resistance includes a semiconductor block having at least two surfaces and a drift region (110) disposed within the semiconductor block; the drift region is characterized by a first conduction type and a first predetermined dopant concentration. A body region (104) with a second conduction type is disposed within the semiconductor block between and adjacent to the first surface and the drift region. A source region (142) is disposed within the semiconductor block, and is embedded in the body region so as to be adjacent to the body region and the first surface. The MOSFET device further includes at least one drain region disposed in the semiconductor block between the second surface and the drift region. An opening is formed in the body region, extending from the first surface and into the semiconductor block. The opening has one or more interior walls (106) that are doped with a dopant of the same conduction type as the body region, and at a second predetermined dopant concentration, so as to form a depletable region near the walls. A blocking voltage applied across the MOSFET device depletes charge carriers within the semiconductor block, so as to substantially prevent electrical current from flowing through the MOSFET between the source region and the drain region. The opening, or trench (102), in the device forces the depletion region to spread laterally within the drift region as blocking voltage increases.
摘要翻译：通过使源极至漏极沟道电阻最小化而显示低功率损耗特性的MOSFET器件（100）包括具有至少两个表面的半导体块和设置在该半导体块内的漂移区（110）; 漂移区的特征在于第一导电类型和第一预定掺杂剂浓度。具有第二导电类型的主体区域（104）设置在半导体块内，并且与第一表面和漂移区域相邻。源极区域（142）设置在半导体块内，并且被嵌入在主体区域中以与身体区域和第一表面相邻。 MOSFET器件还包括设置在第二表面和漂移区域之间的半导体块中的至少一个漏极区域。在本体区域中形成有从第一表面延伸到半导体块中的开口。开口具有一个或多个内壁（106），其被掺杂有与体区相同导电类型的掺杂剂，并且以第二预定掺杂剂浓度掺杂，以在壁附近形成可消耗区域。施加在MOSFET器件两端的阻断电压耗尽半导体块内的电荷载流子，从而基本上防止电流流过源极区和漏极区之间的MOSFET。当阻塞电压增加时，器件中的开口或沟槽（102）迫使耗尽区域在漂移区域内横向扩展。

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